Status of the nXYTER testing

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Status of the n-XYTER testing
CBM

• Knut Solvag, Gerd Modzel, Christian Schmidt,
  Markus Höhl, Andrea Brogna, Ullrich Trunk,
  Hans-Kristian Soltveit

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n-XYTER
The First Dedicated Neutron Detector Readout ASIC
Developed within FP6 For thermal neutron
applications
Is now beeing tested in a cooperation between
Heidelberg, DETNI and CBM
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n-XYTER DETNI Neutron Detector Readout ASIC
Neutron X, Y, Time and Energy ... R
8 LVDS output lines at 4 x 32MHz time stamp,
channel no. 1 differential, analogue output
128 asynchronous analogue inputs at 32
MHz total average input rate
250 dies shared with DETNI collab.
AMS CMOS 0.35µ with thick metal four
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Data Driven Front-End Asynchronous Channel
Trigger
triggertimestamp reg.
comparator
Time WalkCompensationcircuit
FASTshaper 18.5 ns peaking
PDH reset
chargepreamp
dig. FIFO
chargeinput
SLOW shaper(2 stages) 140ns peaking time
Peakdetector hold, free running
pulse height output
analogue FIFO

• 128 channel data driven charge sensitive
  front-end
• Front end for either polarity input signals
• Fast charge sensitive pre-amp and peak detector
• Time stamping with 1ns resolution
• Purely data driven, autonomous hit detection

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Token Ring Readout Process

• Focus bandwidth where there is data
• Automatic zero suppression

token cycle
token cell control logic for data readout or
token pass
Analog FIFO
Disc.
Timestamp FIFO
data readout bus
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n-XYTER 1.0 Testboard

• 64 channels connected
• I²C-Interface
• Test points accessible
• All functional tests possible
• All analogue evaluation possible

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Registers

• 44 registers in total
• Registers are configured by I²C-Bus
• 16 mask registers for shutting down individual
  channels
• 14 adjustment registers for setting
  voltages/currents in the chip
• 13 configuration/status registers
• 1 shift register for local channel threshold
  trimming

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First measurement of the Adjustment registers
Expected (simulation) range 0.928 1.651 V
Measurement range 0.880 1.655 V
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Analogue Pulses, Peaking Time, Front-End Noise
power consumption 12.8 mW for one complete
channel OK for neutrons!
30 pF, giving 1000 (850)e 600 e
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Test modes
Test pulse mode
Test trigger mode

• The analog part is completly circumvented

• The whole chip can be tested without external
  input

• Size of the input charge can be varied

Signal injection Test trigger mode
Charge injection Test pulse mode
comparator
Time WalkCompensationcircuit
triggertimestamp reg.
FASTshaper 18.5 ns peaking
PDH reset
chargepreamp
dig. FIFO
chargeinput
SLOW shaper(2 stages) 140ns peaking time
Peakdetector hold, free running
pulse height output
analogue FIFO
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Noise of the analog channels
Trigger efficiensy of treshold scan
Derivative gives image of noise
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Trigger efficiency for all channelsunshielded
chip
Channel number
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Trigger efficiency for all channels shielded chip
Channel number
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Summary

• Chip is fully functional tested
• No flaws surfaced
• Analog preformance apears to be to specifications

Further testing

• - Conect to silicon strip, and see wether it
  operates sattisfactionary with a detector
  attached
• - Improve test setup
• - Quantitative measurement of the analog output
• Testing of preformance at higher clock
  frequencies
• Homogeneity of the chip