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Readout for the HFT at STAR

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A Stand-alone Heavy Flavor Tracker for STAR. Z. Xu ... Rose, K. Schweda, E. Sichtermann, J.H. Thomas, H. Wieman, N. Xu, and more STARs! ... – PowerPoint PPT presentation

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Title: Readout for the HFT at STAR


1
Readout for the HFT at STAR
2
  • A Stand-alone Heavy Flavor Tracker for STAR
  • Z. Xu
  • Brookhaven National Laboratory, Upton, New York
    11973
  • Y. Chen, S. Kleinfelder, A. Koohi, S. Li
  • University of California, Irvine, California
  • H. Huang, A. Tai
  • University of California, Los Angeles, California
    90095
  • V. Kushpil, M. Sumbera
  • Nuclear Physics Institute AS CR, 250 68
    Rez/Prague, Czech Republic
  • C. Colledani, W. Dulinski, A. Himmi, C. Hu, A.
    Shabetai, M. Szelezniak, I. Valin, M. Winter
  • Institut de Recherches Subatomique, Strasbourg,
    France
  • M. Miller, B. Surrow, G. Van Nieuwenhuizen
  • Massachusetts Institute of Technology, Cambridge,
    MA 02139
  • L. Greiner, H.S. Matis, M. Oldenburg, H.G.
    Ritter, F. Retiere, A. Rose, K. Schweda,
    E. Sichtermann, J.H. Thomas, H. Wieman, N. Xu,
    and more STARs!
  • Lawrence Berkeley National Laboratory, Berkeley,
    California 94720
  • I. Kotov
  • Ohio State University, Columbus, Ohio 43210

3
STAR HFT
  • Two layers
  • 1.5 cm radius
  • 4.5 cm radius
  • 24 ladders
  • 2 cm X 20 cm each
  • 100 Mega Pixels

Purpose Greatly improve D meson capability in
STAR
4
HFT Ladder
  • 10 MimoSTAR detectors / ladder (green)
  • I gt V conversion and driver electronics (blue)
  • All ladders are the same

5
MimoSTAR Detector Pixel Structure
  • Serial raster readout
  • 640 pixels in a row
  • 320 column / sector
  • 2 sectors / detector
  • 4 ms readout time (50 MHz pixel read clock)

Mimosa5 detectors in a wafer
6
I gt V Conversion and driver electronics
  • 20 I gt V converters / drivers per ladder
  • Additional clock, control and JTAG connections.
    Power and ground
  • Analog signals and clock/control is transferred
    to the motherboard via fine twisted pair cable.

7
HFT Readout Functional Goals
  • Digitize every 20 ns.
  • Triggered detector system fitting into existing
    STAR infrastructure.
  • Deliver full frame events to STAR DAQ for event
    building at approximately the same rate as the
    TPC.
  • Reduce the total data rate of the detector to a
    manageable level (ltlt TPC rate)
  • Reliable, robust, cheap, etc.

8
Functional Block Diagram
The readout system is a large parallel system.
The block diagram shown above is for one ladder
of a 24 ladder system.
9
ADC and CDS Block Diagram
  • Synchronous Correlated Double Sampling and hot
    pixel removal.
  • 8 bit data after CDS.
  • Perform read subtract write on each clock
    tick.

10
Cluster Finding FPGA
11
(No Transcript)
12
Cluster FIFO
  • Trigger enables FIFOs sequentially for 1 frame (
    204,800 clocks) with an offset to the enable that
    aligns the event start time with the location of
    the first pixel in the event.
  • Each event FIFO is a separate trigger event
    stream and can be enabled independently. This
    allows events to be triggered at 1 ms intervals
    with our 4 ms latency.
  • Each sector event FIFO is emptied by the SIU at
    the end of the frame.

13
Implementation Diagram
14
Some Relevant Numbers
  • bits/address 18
  • Number of inner ladders 6
  • Number of outer ladders 18
  • Sectors (half chips) per ladder 20
  • ave hits/half chip, inner, (L 1027) 200
  • ave hits/half chip, outer, (L 1027) 40
  • 1 KHz event rate.

15
Data Rates
  • Average event size 90 KB
  • Event size 90 MB/sec at 1KHz
  • 24 fibers
  • 12 RORC (4 readout PCs)

16
Features of HFT Readout Scheme
  • The daughter board hardware will provide the full
    data rate and functionality required for a
    complete first generation 4 ms HFT solution.
  • Much of the required VHDL firm ware is running,
    tested and understood
  • The cluster identifier runs at the same speed as
    digitization providing immediate data
    compression. Only cluster center addresses are
    passed on for data storage.
  • Data digitization and compression takes the same
    4 ms for all events independent of data.
  • The cluster identifier and data compression fits
    well in the FPGA environment. It requires few
    resources and can be implemented with simple
    straight forward VHDL coding.
  • The design is triggered and fits the standard DAQ
    design.
  • All the hits for an event are stored directly for
    that event. There are no complications with
    frame boundaries or hits for an event located in
    different frames. This is important because file
    handling software used in STAR data analysis does
    not have to be altered to accommodate the HFT.
  • The latency is 4 ms, but the dead time is 1 ms
    matching the new TPC system.
  • The HFT data size for an event is 90 kBytes,
    significantly less than the 2 Mbytes for TPC
    central collision event.

17
Data Format
18 bit wide words
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