Datapath Implementation for Maskless Lithography

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Datapath Implementation for Maskless Lithography

• BWRC Retreat
• David Fang, Prof. B. Nikolic
• June 2-3, 2004

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Design Goal Overview
Maskless Lithography Implementation
Mirror Chip Details

• To achieve 10wph given a 10Khz light source
  requires 40.6 million mirrors on the mirror chip
• Aspect Ratio 1800 x 20,000 mirrors

Physical Details

• A single mirror cell is 1.2um by 1.2um which is
  optically focused to a single 45nm feature size
  pixel
• 32 level adjustable levels allow for a 1nm edge
  placement on silicon
• Mirrors are controlled electro-statically via
  tilting comb or parallel plate mirrors which have
  a non-linear displacement response to voltage

Throughput Requirements

• Using an 5-bits per mirror requires a data
  throughput of 1.22 Tbps

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I/O Architecture
Maskless Lithography System
I/O Test Architecture
18 MUX
Cal. Logic
D/A
SRAM Array
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Mirror Structure

• Electro-Static Parallel Plate Mirror
• Non-linear voltage transfer curve
• 1um x 1um mirror dimension for 45nm spots
• Governed by electrostatic equations
• Challenges
• Variations in gap height and flexure membrane
  thickness changes overall voltage response
• Requires up to 2V driver using deep sub-micron
  technology (65nm final scale)

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D/A Specification

• 2V Operating Range
• 272mV error _at_ 0.0V
• 12mV error _at_ 1.8V
• 32 Non-linear Code Levels
• 50ns Write Time (1 DAC/row)
• 5-bit Binary Inputs

Performance
12mV _at_ 1.8V bias

• 1.2 um Row Height
• 1.2um x 1.2um Mirror Area

Area

• Minimize Power
• 1.0V/2.5V Supply Available

Power
Maximum Error Curve
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Nominal Transfer Curve
0?1.8V
32 Positions
Analog Input Voltage versus 5-bit Input Code
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D/A Structure I

• Original Loading Strategy
• Brute Force method
• 8-bit, 2.5V transistor Voltage D/A Converter
• Can be programmable for any mirror response
• Requires decoding for 8-bit inputs or a 5?8
  decoder
• Problems
• 2.5V Transistors are bulky
• Decoder may be too large
• to fit in bit slice
• 2.5V memory cell too large

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D/A Structure II

• Improved Strategy
• Bias zero position at 1V
• Shifts I/O range from 0?1.8V to 1V?2V
• If mirror bottom plate is biased at -1V, D/A
  needs a response from 0?1V
• Tradeoffs
• Mirror has slightly more linear response at those
  voltages
• D/A will have more stringent accuracy
  requirements
• Allows the use of minimum length transistors
• Memory Cell can be built from minimum length
  transistors

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Memory Cell Specification

• Mirror Capacitance can be modeled by a 300aF
  capacitor in series with a 300Mohm load
• Memory Cell must be sufficiently large to
  compensate for charge sharing (10-100x larger
  than mirror capacitance)

• Active gate capacitance and fingered metal 1-5 is
  capable of generating capacitances gt 10fF

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SRAM/Mirror Charge Sharing