Random Number Generator

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Random Number Generator
March 1, 2006 Component Layout and Floorplan

• Dmitriy Solmonov W1-1
• David Levitt W1-2
• Jesse Guss W1-3
• Sirisha Pillalamarri W1-4
• Matt Russo W1-5
• Design Manager Thiago Hersan

Project Objective Create a Cryptologically
Secure Pseudo-Random Number Generator
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Need for Encryption

• Explain how a good random number can make data
  transfer that much more secure.

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Random Number?

• Pseudo-random number generator
• Uses RC4 encryption algorithm
• Cryptographically secure
• Internally Updated Seed
• not in programmer's visible state
• hacker

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Usage
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Demand

• Potential markets
• Defense and Intelligence Organizations
• Gambling
• Component of future secure mobile communications

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The IBAA Algorithm
define ALPHA (8) define SIZE (1ltltALPHA) define
ind(x) ((x)(0x1F)) define barrel(a)
(((a)ltlt19)((a)13)) /beta32, shift19/ yy1b
mind(i)y bmind(ygtgtALPHAx rind(i)b f
or(i0iltSIZEi) Xmind(i) Abarrel(a)mind
(I 16) Y1mind(x)a Yy1b Mind(i)y Bm
ind(y)gtgtALPHAx Rind(i)b
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Algorithm Animation

• TBC

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Algorithm to Architecture

• Explain progression from C code to choice of
  hardware.

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Algorithm to Architecture

• Explain the choice for a 2-Stage Pipeline with
  multiple cycles per stage.

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Algorithm to Architecture

• Explain why 4 cycles per stage yields the best
  throughput under hardware assumptions

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typedef unsigned int u4 / unsigned four bytes,
32 bits / define ALPHA (8) define SIZE
(1ltltALPHA) define ind(x) ((x)(SIZE-1))
define barrel(a) (((a)ltlt19)((a)gtgt13)) /
beta32,shift19 / static void ibaa(m,r,aa,bb)
u4 m / Memory array of SIZE ALPHA-bit terms
/ u4 r / Results the sequence, same size as
m / u4 aa / Accumulator a single value /
u4 bb / the previous result / register
u4 a,b,x,y,i a aa b bb for (i0
iltSIZE i) x mi a barrel(a)
mind(i(SIZE/2)) / set a / mi y
mind(x) a b / set m / ri b
mind(ygtgtALPHA) x / set r / bb b
aa a
SRAM (M)
(M1, M2, M3) Registers
Adder
(X) Reg
(M4) Reg
Counter
Control Logic
FSM
Counter
Register
SRAM (R)
Adder
(B) Reg
(Y) Reg
Adder
(Y1) Reg
Adder
(A) Reg
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Floorplan Evolution 1
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Floorplan 2
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Final Floorplan
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• Animation showing what happens on every cycle of
  the loop.

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DFM ME

• The Rules
• Everything is on a grid
• Everything is mono-directional
• All metal widths are the same
• Contacts same width as metals

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Why DFM

• Easier to perform RET
• Manufacturability
• A must for the new generation of transistor sizes.

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Pros

• Regular Layout
• Enforced Standardization
• More Accurate Resolution
• Contacts match metal widths

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Example Group Propagate
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CONS

• Harder to cut-corners
• More time-involving
• Increased Area
• Decreased Speed
• More Metal Layers
• Learning Curve

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Adder

• Four adders execute 256 times each to generate
  one number.
• Hybrid carry skip, carry look ahead, conditional
  sum,
• Fast and low power.
• Chirca, Schulte, Glossner, et al. A Static
  Low-Power, High-Performance 32-bit Carry Skip
  Adder
• http//mesa.ece.wisc.edu/publications/cp_2004-12.p
  df

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32-Bit Adder
Block Diagram
A2710
B2710
A3128
B3128
A30
B30
A94
B94
C0
C4
C10
C28
C32
CS4
CS18
CS6
CS4
S3128
S2710
S94
S30
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First CS4 Block
32-Bit Adder
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CS18 Block
32-Bit Adder
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32 Bit Fast Adder
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Adder Performance

• Discuss trade offs in speed and power.

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SRAM
Single Bus Cell
Double Bus Cell
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SRAM Single Bus
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Dual Bus SRAM
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Discuss Speed and Power

• SRAM power consumption
• Why we cant do better with the SRAM

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Verification

• Tested architectural verilog against C code for
  matching 1024-bit number results.
• Tested architectural verilog against structural
  verilog for matching port outputs.

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Verification

• Verified Schematic against Verilog implementation
  in cadence
• Made sure that output was the same
• Checked delays and voltage levels
• Verified layout vs. schematic
• Checked levels with parasitics
• Performed LVS test

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(No Transcript)
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Poly Density 7.06
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Metal Density 19.59
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Metal2 Density 18.85
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Metal3 Density 19.24
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Metal4 Density 8.91
Metal5 Density 4.75
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Critical Delay
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Specs

• Pins
• 40 input pins (including clock, vdd, gnd)
• 32 output pins (the random number)
• 475 MHz chip speed
• 436 KHz throughput

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Putting it All Together
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Questions