FAST : FrequencyAware Static Timing Analysis

1
FAST Frequency-Aware Static Timing Analysis

• Kiran Seth
• Aravindh Anantaraman
• Frank Mueller
• Eric Rotenberg
• 2003 IEEE Real-Time Systems Symposium

2
Introduction

• Real Time DVS
• Reduce the frequency/voltage of the processor
  while still meeting deadlines for energy savings
• WCET of each task has to be known in advance
• Static Timing Analysis
• A technique which collects information about the
  program structure and timing metrics at compile
  time
• Has to provide the means to derive safe and tight
  WCET bounds

3
Introduction (cont.)

• The Assumption of General STA
• Reducing a processors frequency results in the
  same number of cycles of execution for a task
• Does not hold for realistic architectures.

Memory
Processor
Overestimated
Original
Memory
Processor
Expected
Processor
Memory
Real
Deadline
Time
4
Introduction (cont.)

• Different WCET values for each processor
  frequency/bus frequency pair have to be obtained
• Frequency-aware static timing analysis (FAST)
• Expresses WCET bounds as a parametric term
• Determines on-the-fly the WCET for a given
  frequency pair

5
Parametric Frequency Model
WCEC i mN

• i
• The ideal number of cycles required to execute
  the task assuming perfect caches
• Does not scale with the processor frequency
• m
• The total number of I/D cache misses for the task
• Independent on the processor frequency
• N
• The number of cycles required to access the
  memory
• Scales with the processor frequency
• fprocessor L

6
Parametric Frequency Model (cont.)

• I miss in B (N10)

• WCEC 9 1N

7
Parametric Frequency Model (cont.)

• D miss in B (N10)

Overlap

• With the overlap, WCEC 9 1N

• Without the overlap, WCEC 10 1N
• This model does not consider the overlap!

8
Static Timing Analysis

• STA tool calculates the WCEC for a particular
  task
• Path analysis selects the longest execution path
• Whenever the processor frequency is changed, the
  WCEC information for different paths changes
• May result in a different worst-case path than
  before

9
FAST

• The parametric frequency model (WCEC i mN) is
  incorporated into STA
• FAST calculates the number of cycles for each
  possible worst-case path

WCEC
A
C
B
fprocessor
10
FAST (cont.)

• Maintain an ordered list of equations and the
  ranges where the equation represent a larger WCEC
  than previous ones
• Difficult to apply to DVS algorithms

WCEC
A
C
B
0
a
b
max
fprocessor
11
FAST (cont.)

• Make a curve-fitting equation
• The resulting curve would not be tight
• Impose more overhead on dynamic scheduling schemes

BC
WCEC
A
C
B
fprocessor
12
FAST (cont.)

• Declare a valid range of frequencies
• If two equations intersect within this specified
  range, use a simple curve-fitting technique
  through a first-order polynomial

WCEC
A
C
B
fprocessor
13
FAST-DVS Schemes

• In EDF-based DVS algorithms by Pillai and Shin
• a fc/fm
• fc the scaled frequency
• fm the peak frequency

• WCEC i mN, N L f
• Cj (ij mjLf)f, f afm

14
FAST-DVS Schemes (cont.)

• FAST ccEDF DVS

15
Experimental Framework

• Implement of FAST tool
• Based on the PISA used by the SimpleScalar
• Input
• The control-flow graphs and instruction layouts
• Output
• The WCEC in the form of a parametric equation
• A constant memory latency of 100ns is used
• I-Cache analysis
• The static cache simulator is used
• D-Cache analysis
• Assume a constant number of data accesses as
  misses and the remaining references as cache hits

16
Results

• FAST vs. Traditional WCEC

17
Results (cont.)

• Testing FAST-DVS Schemes

Utilization 0.9
Utilization 0.5
18
Conclusion

• This paper presents the FAST scheme providing
  frequency-aware bounds on the WCET through static
  timing analysis
• FAST can derive safe upper bounds on the WCET,
  which are almost as tight as non-parametric
  timing analysis
• FAST equations can be used to improve existing
  DVS scheduling schemes