VLSI TESTING

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VLSI TESTING

• DESIGN FOR TESTABILITY
• FAULT DETECTION TECHNIQUES

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DEFINITION OF TESTING

• Testing in its broadest sense means to examine a
  product and to ensure that it functions and
  exhibits the properties and capabilities that it
  was designed to possess.
• Main purpose of testing is to detect malfunctions
  in the product hardware and to locate their
  causes so that they may be eliminated.
• Testing terms
• OtbT object to be tested
• DUT device under test
• CUT circuit under test
• Ls Latches
• CN Combinational Networks

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CONVENTIONAL TEST METHODS

• These rely primarily on mechanical means and not
  on use of additional circuits in an otbT for the
  purpose of facilitating its testing. Examples
  include use of extra I/O for additional test
  points, improvement of test features.
• Characteristics
• They are used for testing system parts only
  outside the system.
• They rely on feeding signals directly through the
  test interface during listing.
• They rely on the use of tester-driven timing.

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DIFFICULTIES IN TESTING

• Shortage of I/O points.
• Signal distortions in interface connections.
• Noise disturbances.
• Uncertainties in input feeding.
• Uncertainties in output sensing. (Rejection of
  good parts reduces apparent yield.)
• Difficulty in synchronizing test objects timing
  with tester timing.
• High costs for test equipment ,test generation
  and execution.
• Large volume of data to be processed.

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FAULTS

• If anything can go wrong, it will.
• Murphys Law

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FAULT DEFINITION

• In any circuit composed of logic gates, there
  is the possibility of the occurrence of a fault.
  A fault is defined to have occurred when a
  circuit variable assumes a value(1,0 or X) which
  differs from that expected that is violates the
  original circuit equation.
• Fault Types
• SAO Stuck at 0 (short with ground rail)
• SA1 Stuck at 1 (short with Vdd)

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FAULT TYPES AND MODELS

• Examples of physical defects include
• Defects in silicon substrate.
• Photolithographic defects.
• Mask contamination and scratches.
• Process variation and abnormalities.
• Oxide defects.
• Electrical faults caused
• Shorts, opens, transistor stuck-on or stuck-off,
  Resistive shorts and opens, Excessive change in
  threshold voltage and excessive change in steady
  state currents.

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KINDS OF FAULTS

• Single faults
• Multiple faults.

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CIRCUIT FOR AO1
EQUATIONS X7X6X5 X5X1.X2
X6X3.X4 X7X1.X2X3.X4
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KINDS OF FAULTS

• Single faults
• Multiple faults.
• No of single fault locations 7
• No of single faults 2 7 14
• No of double fault combs. 2 2 7C2 84
• Fault combinations are not unique. A test for
  SA0 at x1 also covers SA0 at x5 and x7.

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FAULT EQUIVALENCES

• One or more inputs to an OR gate at SA1 is
  equivalent to an OR gate whose output is at SA1.
• One or more inputs to an AND gate at SA0 is
  equivalent to an AND gate whose output is at SA0.
• All inputs to an OR gate at SA0 is equivalent to
  an OR gate whose output is at SA0.
• All inputs to an AND gate at SA1 is equivalent to
  an AND gate whose output is at SA1.
• Thus any gate output fault has an equivalent
  single stuck fault or multiple stuck fault.

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MASKING OF FAULTS

• Definition
• Let Tg be a test that detects a fault g. We can
  say that a fault f functionally masks the fault g
  iff the multiple faults (f,g) is not detected by
  any test in Tg.

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SINGLE STUCK FAULT MODEL

• Single stuck-fault model (SSF) is the classical
  or standard fault model. Its usefulness results
  from the following attributes
• it presents many different physical faults
• it is independent of technology
• compared to other fault models, the number of
  SSFs in a circuit is small
• SSFs can be used to model other type of faults.

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AND-NAND BLOCK

• XAND(A,B,C,D) YNAND(A,B,C,D)

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• The test sequence can thus be obtained by
  finding out the combinations.
• Complementary circuits can be tested in the
  similar fashion.
• For a single stack model containing N nodes,
  where in each node can be in one of the 3 states
  (good,SA0,SA1) 3N combinations are possible. For
  N100 we get 5.1047 combinations which is a very
  large data to process.

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EXISTENCE FUNCTION

• Developing a test sequence
• x6x3.x4
• x5x1.x2
• x7x5x6
• Rules for labeling the nodes
• Primary inputs are labeled with the lowest
  indexed variables.
• Fan outs are labeled separately.

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CIRCUIT FOR AO1
EQUATIONS X7X6X5 X5X1.X2
X6X3.X4 X7X1.X2X3.X4
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EQUATIONS

• Fi(x0,x1.xp)Gi(xo,x1.xp)
• F G
• ?F.G ?G.F 0
• where F is the set of inputs and G is the set of
  outputs.
• F G
• x1.x2 x5
• x3.x4 x6
• x5x6 x7
• ?F.G x5x1x2 x6x3x4 x7x5 x7x6
• ?G.F x5x1 x6x3 x5x2 x6x4 x7x6x5

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EXISTENCE FUNCTION GENERATOR

• Mark all the points which are covered by at
  least one of the terms. Instead of 7 variable K
  map use a Marquand chart.
• After cancellation, take the remaining points.
  These are the ones in the existence function
  circuit. ( No of ones 16).
• Move from one point to a place where there is a
  change in output.

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• Longest chain will produce the desired test
  sequence. The complete test sequence is
• 5-7-6-14-10-11-9-13-5.
• Each of the input variables is tested
  independently for a change in value from 0 to 1
  and again from 1 to 0. Each of the intermediate
  variable is also tested in the process.
• Each output variable is thereby tested for its
  ability to change value from a 1 to 0 and from a
  0 to 1.

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ADVANTAGES OF TEST SEQUENCES

• Test sequence can be produced by a hardware unit
  instead of the usual software unit.
• Continuous resetting between tests is not
  necessary.
• Since at least one of the outputs change on the
  application of an input, detection of a failure
  is logically straightforward.
• The test sequence covers all detectable single
  faults.
• The test sequence is closed i.e it returns to the
  initial state. This helps in reducing resetting.

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DRAWBACKS OF SINGLE STACK FAULT MODEL

• Does not take into account other kinds of faults
  such as
• AC-faults.
• Bridging circuits.
• Faults in CMOS circuits.
• Multiple faults simultaneously presented in the
  system.

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DESIGN FOR TESTABILITY

• Testable means capable of being ascertained as
  being fault free or not.
• The aim of testability is to make the parts
  testable not only on test fixtures separately
  from the system but also within the system when
  the parts are connected.
• It should also include diagnosability i.e the
  capability of locating faults at least down to
  the smallest repair-replaceable unit

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THREE KEY FUNCTIONS

• Control
• Setting the conditions for the tests so that
  stimuli can be supplied to the object to be
  tested.
• Observation
• Obtaining the response to the stimuli so that
  the behavior can be evaluated.
• Isolation
• Making the control and observation possible and
  more reliable.

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TECHNIQUES

• Ad-hoc Testable Design Techniques
• Initialize sequential circuit
• Avoid redundancy logic
• Avoid asynchronous logic
• Avoid redundant circuits.
• Built in Self Testing. (BIST)

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AD-HOC DESIGN

• The three main features are
• Partition and Multiplexer techniques.
• Use of switches
• Ex For a 32 bit counter checking is very
  difficult. But if we have sub-circuits ,testing
  will be easier.
• Switches will be placed throughout.

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PARTITION TECHNIQUE
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BUILT IN SELF TECHNIQUES

• In built-in-self-techniques (BIST) parts of the
  circuits are used to test the circuit itself. On
  line BIST is used to perform test under normal
  operation where as off line BIST for testing
  offline.
• Components
• Pseudo Random Pattern Generator (PRPG)
• Output Random Analyzer (ORA)

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BUILT IN SELF TEST
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OUTPUT RANDOM ANALYZER

• Cyclic Redundancy Check
• G(x) Q(x) P(x) R(x)
• where P(x) is the characteristic polynomial
  (output of the CUT).
• R(x) is the remainder and Q(x) is the quotient.
• P(x) x5 x4 x2 1
• G(x) with the sequence 1 1 1 1 0 1 0 1
• G(x) x7 x6 x5 x4 x2 1 and
• R(x) x4 x2 which corresponds to the
  register(0 0 1 0 1)

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• The on chip storage of a fault dictionary
  containing all the test inputs with the
  corresponding outputs is prohibitively expensive
  in terms of the chip area.
• Alternative is to compare the outputs of 2
  identical circuits for the same inputs assuming
  that the probability that the two devices will
  have the same kind of faults is less.

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END