BWRC IC Design Flow

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BWRC IC Design Flow

• Concept Slides
• last updated 3/9/00
• by Rhett Davis

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CMOS density now allows complete
System-on-a-chip Solutions
Also like to add

• FPGA
• Reconfigurable Interconnect

How do we design these chips?
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Possible Single-Chip Radio Architectures

• Software-Centric
• GOAL Simplify System Design Process
• Seek architectures which are flexible such that
  more time can be spent optimizing the hardware.
• APPROACH Minimize the use of dedicated logic

• Hardware-Centric
• GOAL Maximize Bandwidth Efficiency and Battery
  Life
• Seek architectures which perform complex
  algorithms very fast with minimal energy
• APPROACH Minimize the use of programmable logic

Can we do both?
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The Industry Standard ASIC Design Flow

• Difficulties
• Logic Verification
• Timing Closure
• Routing Congestion

Problem Indeterminate Design Time

• Design Decisions made at Every Step
• Unsolvable Problems Arise

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Our Approach

• Develop a Design Flow
• Fully Automated
• Restrict all decisions to beginning
• Demonstrate on at least two chips
• Direct-Mapped Radio Micro-Architecture
• Compare to other chips and flows

Key Challenge Demonstrate Functionality without
Sacrificing Performance
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Use A Formal Design Flow Syntax
A Design Flow is a directed, acyclic graph

• Each node is a step. A step has associated with
  it a file or ordered list of files
• A step with one or more outgoing edges is a
  dependency
• A step with one or more incoming edges is a
  target. Each target has associated with it a
  command to update the file(s) from the
  dependencies
• A step can contain another design flow

This framework allows us to document, automate,
and evaluate design flows
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Simulink is a good Starting Point
Simulink Improves Interaction among Disciplines
A Simulink Model can also be used as a complete
Functional Specification
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Netlisting Mapping Simulink to Physical
Physical design hierarchy matches the logical
design hierarchy
Simulink Name scr1/SCR1/Filter/Filter200_1 Simuli
nk Library Link dec_filter_lib/Filter200 Physical
Library Name dec_filter_lib Physical Cell
Name Filter200 Physical Instance Name
Filter200_1
Simulink Name scr1/SCR1 Physical Library Name
top Physical Cell Name SCR1
Simulink Name scr1/SCR1/Filter Physical Library
Name top Physical Cell Name
SCR1_Filter Physical Instance Name Filter
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Elaboration Mapping Macros to Abstracts

• Modules
• Stateflow

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Microprocessor Macros

• Includes
• Processor
• Memory
• Bus
• Interface
• Hard Soft Cores
• Automatic Code Generation

Microprocessor Macros map to a more general
combination of abstracts
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Minimized Floor-planning

• The Simulink Designer is responsible for creating
  the floor-plan in DesignPlanner with the
  following functions
• Draw Standard Cell Rows
• Align
• Distribute/Compact
• Boundary Compaction
• The floor-plan contains placement information
  only.

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Example Floorplan
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The Current Flow