Using Contrapositive Law in an Implication Graph to Identify Logic Redundancies

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Using Contrapositive Law in an Implication Graph
to Identify Logic Redundancies

• Kunal K. Dave
• ATI Research INC.
• Vishwani D. Agrawal
• Dept. of ECE, Auburn University
• Michael L. Bushnell
• Dept. of ECE, Rutgers University

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About this work !!!

• This work is motivated by a fault independent
  redundancy identification method using
  implication graphs.
• We use contrapositive rule to derive new partial
  implication nodes, oring nodes, to enhance the
  logic information in the implication graph.
• Develop new algorithms that dynamically update
  the transitive closure graph while extracting
  implications from a logic network described in
  the paper and Masters thesis.
• Apply new implication graph and dynamic update
  algorithms to redundancy identification to obtain
  better performance.

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Implication Graph

• An implication graph (IG) ? Digital circuit in
  the form of a set of binary and higher-order
  relations.

Boolean equation AND c ab
a
c
Implication graph with with anding nodes
b

• Chakradhar et al. -- IEEE-DT, 1990
• Henftling and Wittmann AEU, 1995

c
a
b
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Observability Implications
a
c
b
Oc
Oa
Observability nodes Agrawal, Lin and Bushnell
-- ATS, 1996
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Transitive Closure

• Transitive closure (TC) of a directed graph
  contains the same set of nodes as the original
  graph.
• If there is a directed path from node a to b,
  then the transitive closure contains an edge from
  a to b.

A Graph
Transitive Closure
b
a
a
b
c
c
d
d
Transitive closure
A graph
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Oring Nodes
Expansion of Boolean false function AND ac bc
abc 0
De-Morgan
Contrapositive
(a ? b) c
c (a V b)
Enhanced Implication graph (previous)
New Implication graph (present)
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Redundancy Identification

• Obtain an implication graph from the circuit
  topology and compute transitive closure.
• There are 8 different conditions on the basis of
  which a fault is said to be redundant.
• Examples
• If node c implies c then s-a-0 fault on line c is
  redundant.
• If node Oc implies Oc then c is unobservable and
  both s-a-0 and s-a-1 faults on line c are
  redundant.
• No Search is performed to find redundant faults.
• A Subset of total redundant faults is found.

Agrawal et al. -- ATS, 1996 Gaur et al. --
DELTA, 2002
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An Example
s-a-0 s-a-1
a
c
Portion of the implication graph containing
controllability nodes (Observability nodes are
not shown)
b
s-a-0
e
s-a-0 s-a-1
d
e
a
c
d
b
?1
?2
?3
a
e
c
d
b
?4
V1
V2
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Results on ISCAS Circuits
Circuit Total faults Redundant faults identified and run time Redundant faults identified and run time Redundant faults identified and run time Redundant faults identified and run time Redundant faults identified and run time Redundant faults identified and run time Redundant faults identified and run time Redundant faults identified and run time
Circuit Total faults TRAN Chakradhar et al. TRAN Chakradhar et al. FIRE Iyer and Abramovici FIRE Iyer and Abramovici TCM Mehta et al. TCM Mehta et al. Our Algorithm Our Algorithm
Circuit Total faults Red. faults CPU Sec.a Red. Faults CPU Sec.b Red. Faults CPU Sec.a Red. Faults CPU Sec.a
c1908 1879 7 13.0 6 1.8 2 3.2 5 5.7
c2670 2747 115 95.2 29 1.5 59 4.0 69 6.0
c7552 7550 131 308.0 30 4.7 51 11.5 65 17.7
s1238c 1355 69 17.4 6 1.9 20 2.6 51 5.4
aSun SPARC5 CPU Sec.
bSun SPARC2 CPU Sec.
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ISCAS 85 -- C1908
Redundant faults (s-a-1)
952
949
0/1
0
979
953
887
926
0
74
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ISCAS 85 -- C5315
Redundant fault (s-a-1)
PI
1
0
0
0/1
0/1
1
1
PI
1
0/1
0/1
PO
0
0
0
1
1
1
1
1
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ISCAS 85 -- C5315
Redundant fault (s-a-1)
PI
1
1
0/1
0/1
0/1
1
1
PI
0
0
0/1
PO
1
1
1
0
1
0
0
1
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Conclusion Future Work

• Contributions
• New partial implication structure called oring
  node enhances implication graph of logic
  circuits more complete and more compact than the
  graph with just anding nodes.
• New algorithms dynamically update the transitive
  closure every time a new implication edge is
  added greater efficiency over complete
  re-computation.
• New and improved fault-independent redundancy
  identification.
• New techniques can be further explored
• Fanout stem unobservability proposed solution.
• Equivalence checking.
• Test generation.
• Redundancy removal only one fault is removed at
  a time.

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Thank You