CS 2200 Lecture 2 Instruction Set Architectures ISAs

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CS 2200 Lecture 2Instruction Set Architectures
(ISAs)

• (Lectures based on the work of Jay Brockman,
  Sharon Hu, Randy Katz, Peter Kogge, Bill Leahy,
  Ken MacKenzie, Richard Murphy, and Michael
  Niemier)

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First, a two slide review
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What well cover here

• Broad exposure to computer systems
• Organization of the processor
• Memory hierarchies
• Storage devices
• Parallel processors
• Networking hardware
• SW abstractions in the OS for orchestrating their
  usage
• Networking protocols to connect the computer
  system to its environment
• Major topics
• Processor, Memory Hierarchies, I/O Subsystems,
  Parallel Systems, Networking

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A summarizing picture
CS2130, CS1xxx,
ECE2030
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Second, a roadmap and background
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Our Road Map
Processor
Memory Hierarchy
I/O Subsystem
Parallel Systems
Networking
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Five classic components (of an architecture)
Things well talk about today will deal
with datapath memory (at least indirectly!)
(i.e. well look at this part of the processor)
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What does the processor do?

• Knows where it is in program
• Can get and put data into memory
• Can do some arithmetic
• Can make tests and take different paths depending
  on the results
• Do you need a language to make a computer run?

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A Little History

• First computers programmed by hand
• 1000110010100000
• (Logic gates are switches you can think of 1s
  and 0s as saying that a switch is on or off)
• Somewhat tedious, so invented
• Assembler
• add A,B
• Symbolic representation would be converted to 1s
  and 0s automatically
• (can do similar things like sub, xor, and, etc.)
• If we can convert from Assembly Language to
  machine code why not from some higher level
  language to Assembler?
• A B

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Back to the Instruction Set Architecture

• 1000110010100000
• Why study at this level?
• Common focal point
• Fancy way of saying that this is the 1st link
  between your C code and logic gates
• Thinking about add A, B and 1s and 0s

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Instruction Set Architecture
Another view of the previous picture
Discussion Intel machines legacies
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Instructions

• Language of the machine
• Vocabulary is the instruction set
• i.e. and, xor, store, jump, etc.
• Two levels
• Human readable
• Machine readable
• Most are similar
• What are the goals?
• (for processor design in terms of Boolean gates
  in context of ISAs)
• Note we wont get into gates too much here
  well mainly think in terms of black boxes

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Instructions

• Language of the machine
• Vocabulary is the instruction set
• i.e. and, xor, store, jump, etc.
• Two levels
• Human readable
• Machine readable
• Most are similar
• What are the goals?
• (for processor design in terms of Boolean gates
  in context of ISAs)
• Note we wont get into gates too much here
  well mainly think in terms of black boxes

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Processor Design Goals
Maximize Performance
Lets think in terms of a service analogy
Can we have them all?
Easy to build hardware
Easy to build Complier(s)
(FYI, also works with dating potential dates
are usually attractive, intelligent and available
but you can only pick 2)
You can have something fixed well, fast, and
cheap but can only pick 2.
Minimize Cost
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Beyond Mips

• The textbook (PH) tends to focus on the design
  of the Mips processor with the eventual goal of
  producing a pipelined design (more later).
• Well do this later too
• Many other architectures have been developed and
  used over the last 50 years
• Why?
• Also, ND (MIPS and a similar DLX) GT examples
  (the LC 2200)

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First, a quick overview

• So generally were going to talk about the
  following in the next lecture or 2
• Type of ISAs and assessment techniques for them
• Where does the compiler fit in to all of this?
• A foundation ISA for other parts of this course
• Lots of ISA examples

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Instruction Set Architectures in Detail
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ISAs

• So, whats this thing called an ISA?
• Basically, the portion of machine visible to the
  programmer or compiler writer typically
  assembly code-esq.
• (And easily transferable to 1s, 0s, executables)
• How familiar are people with assembly code?
• There are lots of things to consider when
  studying or designing one
• Hows information stored in or transported to the
  CPU?
• Whats a typical workload for the machine
  designed?
• What are the performance requirements?
• Etc., etc. etc.

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Different types of ISAs

• Determined by means for storing data in CPU
• The major choices are
• A stack, an accumulator, or a set of registers
• Stack architecture
• Operands are implicitly on top of the stack
• Accumulator architecture
• One operand is in an accumulator (register) and
  the others are elsewhere
• (Essentially this is a 1 register machine)
• General purpose registers
• Operands are in registers or specific memory
  locations

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1st, recall this picture
Well talk about stack, accumulator, and general
purpose register machines in pictures ?
particularly the datapath and memory components
(well also go through C-code to
assembly language examples too)
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Now, what might a stack-based dataflow look like?
(see board for ex.)
Stack Pointer
Memory
PC
IR
Stack Top
Address
Why might we need all of these to form an
address???
Flag
Could do an operation with stack top and a value
from memory
1 Stack Top contains value 0 Stack Top is
empty
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What might an accumulator dataflow look like?
(see board for ex.)
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What might a register-based dataflow look like?
OP
i
j
k
Register Write
Memory
Multi-port Register File
Left Register Read
Right Register Read
i ? j op k
Whats wrong with this picture???
(see board for ex.)
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Pros and cons for each ISA type
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So what do people really use?

• Early machines used stack/accumulator
  architectures
• Today, general purpose register (GPR) machines
  are the norm
• Why?
• Registers are internal to CPU faster than
  memory
• Compilers can target code to register based ISA
  better
• i.e. Id rather say, ADD A, B then Push A, Push
  B, Add, Pop and no, I never liked HP
  calculators
• A segment of code like (AB) (CD) (EF)
  can be executed in any order on stack most go
  left-to-right
• Registers can hold
• Variables
• Reduce memory traffic
• Speed up program

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So lets focus on register-based architectures

• 2 major instruction set characteristics divide
  general purpose register architectures
• (1) How many ALU operands are registers?
• Option 1 2 operand format one
  operand/register is a source and destination for
  the operation
• Option 2 3 operand format two source
  registers, one destination register
• (2) How many ALU operands are memory addresses?
• May vary from 0-to-3

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Register and Memory Operands
(m, n) m memory operands and n total operands
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Review (and another way of looking at different
types of architectures in code)
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Instruction Set Classification (to recap)

• One way
• Number of operands for typical arithmetic
  instruction
• add s1, s2, s3

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• What are the possibilities?
• (well review them next in a different way than
  before)
• Will use this C statement as an example
• a b c
• Assume a, b and c are in memory

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Zero Address Machine
0

• a.k.a. Stack Machines
• PUSH b Push b onto stack
• PUSH c Push c onto stack
• ADD Add top two items
• on stack and replace
• with sum
• POP a Remove top of stack
• and store in a

Advantages
Disadvantages
Lack of random access Efficient code hard to
get Stack if often a bottleneck
Short instructions Good code density Simple to
decode instruction
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One Address Machine
1

• a.k.a. Accumulator Machine
• One operand is implicitly the accumulator
• LOAD b ACC ? b
• ADD c ACC ? ACC c
• STORE a a ? ACC

Advantages
Disadvantages
Minimal internal state Short instruction Simple
to decode instruction
Very high memory traffic
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Two Address Machine
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• a.k.a. Register-Memory Instruction Set
• One operand may be a value from memory
• (unlike the Mips architecture discussed in your
  book)
• (and that well learn more about here)
• Machine has n general purpose registers
• 0 through n-1
• LOAD 1, b 1 ? Mb
• ADD 1, c 1 ? 1 Mc
• STORE 1, a Ma ? 1

Advantages
Disadvantages
Data accessible without loading Inst. format easy
to encode Inst. format good density
Operands not equivalent Source operand in binary
operation is destroyed
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Two Address Machine
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• a.k.a. Memory-Memory Machine
• Another possibility do stuff in memory!
• These machines have registers used to compute
  memory addresses
• MOVE a, b Ma ? Mb
• ADD a, c Ma ? Ma Mc

Advantages
Disadvantages
Most compact Doesnt waste reg. for temps.
Memory accesses create bottlenecks
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Two Address Machine
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• a.k.a. Load-Store Instruction Set or
  Register-Register Instruction Set
• Typically can only access memory using load/store
  instructions
• LOAD 1, b 1 ? Mb
• LOAD 2, c 2 ? Mc
• ADD 1, 2 1 ? 1 2
• STORE 1, a Ma ? 1

Advantages
Disadvantages
Data accessible without loading Inst. format easy
to encode Inst. format good density
Operands not equivalent Source operand in binary
operation is destroyed
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Three Address Machine
3

• a.k.a. Load-Store Instruction Set or
  Register-Register Instruction Set
• Typically can only access memory using load/store
  instructions
• LOAD 1, b 1 ? Mb
• LOAD 2, c 2 ? Mc
• ADD 3, 1, 2 3 ? 1 2
• STORE 3, a Ma ? 3

Advantages
Disadvantages
Simple, fixed length instructions Simple code
generation model Similar of clock cycles to
exec.
Higher instruction counts