ECE530: HIGH PERFORMANCE VLSIIC SYSTEMS STUDY OF LOW POWER CMOS DESIGN

1
ECE530 HIGH PERFORMANCE VLSI/IC SYSTEMS STUDY
OF LOW POWER CMOS DESIGN

• By
• ADESH ANKUSH GHADGE

2
OVERVIEW

• Motivation
• Sources of power dissipation
• Techniques for Power Reduction
• Various circuit designs implemented in order to
  get low power
• Algorithm for Low Power Design
• Conclusion

3
WHY GO FOR LOW POWER CMOS

• DRIVING FACTOR OR MOTIVATION
• High functionality and high performance devices
  at low cost
• More transistors, faster and smaller are packed
  into a chip
• Reduction of the power in high performance
  systems (Large integration density High clock
  frequencies) gt (Excessive power dissipation)
• Increase in the cost of cooling and fans for heat
  removal
• Craving for smaller, lighter and more durable
  products
• Increased market for portable consumer
  electronics powered by batteries
• e.g. laptop computers, digital personal
  communication services having portable multimedia
  terminals

4
TREND IN POWER CONSUMPTION OF ICS
Ref1
5
SOURCES OF POWER CONSUMPTION
6
TOTAL POWER DISSIPATION

• 3 Major sources given by equation
• Ptotal a(CL.V.Vdd.fclk) Ileakage.Vdd
  Isc.Vdd
• 1st term represents dynamic power dissipation due
  to charging and discharging of the load
  capacitance
• 2nd term is the subthreshold leakage or static
  power dissipation
• 3rd is the short circuit power dissipation due to
  the direct path short circuit current Isc

7
DYNAMIC POWER DISSIPATION

• Pdyn a(CL.V.Vdd.fclk)
• Can be reduced by reducing either of the above
  components.
• Minimize total switching capacitance, supply
  voltage, and frequency of transitions.
• SHORT-CIRCUIT POWER DISSIPATION
• Psc ISC.Vdd
• Short circuit currents occur when the rise/fall
  time at the input of a gate is larger than the
  output rise/fall time.
• There is a conductive path open because both
  devices are on.
• If Vdd lt Vtn Vtp short-circuit currents
  will be eliminated.

Ref2
8
STATIC POWER DISSIPATION

• Pstatic Ileakage.Vdd
• Determined by the leakage current through each
  transistor.
• Static current, results from resistive paths
  between power supply and ground.

Ref4
9
TECHNIQUES FOR REDUCTION OF POWER DISSIPATION

• Power Supply Voltage Reduction
• Optimizing Threshold Voltage (Vt)
• Using Low-Swing circuit for clock system
• Using new materials as Gate Oxides to reduce
  leakage current
• Avoid unnecessary activity

10
POWER SUPPLY AND THRESHOLD VOLTAGE REDUCTION

• Energy per operation can be reduced by lowering
  the power-supply voltage.
• Speed of the basic gates will also decrease with
  this voltage scaling.
• To counter the performance loss lowering of power
  supply is generally accompanied by lowering the
  Vth.
• Scaling the threshold voltage can limit this
  performance loss somewhat but results in
  increased static power dissipation.

Ref8
11
Continued.

• Typically, circuits are designed at VDD 3.3V
  10 and Vth 0.55 0.1 V
• Circuit speed becomes the slowest at the corner A
  while at the corner B power dissipation becomes
  the highest.
• Better tradeoffs between speed and power can be
  found by reducing fluctuations of Vdd and Vth
  especially in low Vdd.
• For example, at Vdd 2.1V 5 and Vth 0.18V
  0.05 V power dissipation can be reduced to about
  40 while maintaining the circuit speed.

Ref12
12
MULTIPLE THRESHOLDS CMOS DESIGN TECHNIQUES

• Multi-threshold Voltage
• CMOS (MTCMOS)
• Insert high threshold devices in series to
  low-Vth circuitry
• In the active mode, SL is set low and sleep
  control high-Vth transistors (MP and MN) are
  turned on.
• In the standby mode, SL is set high, MN and MP
  are turned o and the leakage current is low.

Ref4
13
MODIFICATIONS IN MT-CMOS

• One type of high Vth transistor is enough for
  leakage control.
• NMOS insertion scheme is preferable, since the
  NMOS on-resistance is smaller.

Ref4
14
DUAL THRESHOLD CMOS
Ref4

• Higher threshold voltage can be assigned to some
  transistors in non-critical paths so as to reduce
  leakage current.
• Low threshold transistors in the critical path(s)

15
DT-CMOS Contd.
Ref4

• Not all the transistors in non-critical paths can
  be assigned a high threshold voltage.
• Gate-level and transistor-level algorithms should
  be used to find out the optimum number of gates
  to be assigned high threshold voltage.

16
VARIABLE THRESHOLD CMOS (VTMOS)

• Uses body-biasing design technique.
• A self-substrate bias circuit is used to control
  the body bias.
• In active mode, a nearly zero body bias is
  applied.
• In standby mode, a deeper reverse body bias is
  applied to increase threshold voltage

Ref4
17
DYNAMIC THRESHOLD CMOS (DTMOS)

• The threshold voltage is altered dynamically to
  suit the operating state of the circuit.
• A high threshold voltage in the standby mode
  gives low leakage current.
• A low threshold voltage allows for higher current
  drives in the active mode of operation.

Ref4
18
ELASTIC VARIABLE THRESHOLD CMOS (EVTMOS)

• Controls both VDD and VBB such that when VDD is
  lowered VBB becomes that much deeper to raise
  VTH.
• Requires very large transistors.

Ref8
19
MULTIPLE VDD CMOS DESIGN TECHNIQUE

• High supply voltage can be assigned to the gates
  in critical path(s).
• While some gates in non-critical path will have
  lower supply voltage.
• Dual-Vdd and dual-Vth techniques can be combined
  to further reduce the dynamic power and leakage
  power

Ref4
20
VARIABLE SUPPLY-VOLTAGE SCHEME

• It consists of three parts 1) a buck converter,
  2) a timing controller, and 3) a speed detector.
• The buck converter generates (N/64).VDD for the
  internal supply voltage VDDL.
• The timing controller calculates N by
  accumulating numbers provided from the speed
  detector.
• The speed detector monitors critical path delay
  in the chip by its replicas under VDDL

Ref12
21
IMPLEMENTING VARIABLE SUPPLY VOLTAGE SCHEME WITH
VTCMOS

• A 32-b RISC core processor R3900
• Ext. Vdd 3.3V 10
• Int. Vdd 0.8V-2.9V 5

Ref12
22
LOW-SWING CLOCK TECHNIQUES FOR CMOS

• Notice that a clock system and a logic part
  itself consume almost the same power in various
  chips.
• Clock system consumes 20 to45 of the total chip
  power.
• To reduce the clock system power, it is effective
  to reduce a clock voltage swing

Ref8
23
LOW-SWING CLOCK DOUBLE-EDGE TRIGGERED FLIP-FLOP
(LSDFF)

• Composed of a data-sampling front end (P1, N1,
  N3N6, I1I4) and a data-transferring back end
  (P2, N2, I9, I10).
• Internal nodes of LSDFF switch only when the
  input changes.
• To prevent performance degradation of the LSDFF
  due toreduced clock swing, low- Vt transistors
  are used for the clocked transistors (N3N6).
• The leakage current of transistors N3N6 will be
  limited by a turned-off high-Vt transistor,
  either P1 or N1 according to input data D

Ref13
24
SIMULATION RESULTS OF LSCDFF

• For an average input switching activity of 0.3,
  the power consumption of LSDFF is reduced by
  28.6-49.6 over conventional FFs.

Ref13
25
NITRIDE-SANDWICHED-OXIDE GATE INSULATOR FOR LOW
POWER CMOS

• SiO2 is now failing to meet the leakage current
  requirements posed by low power CMOS devices.
• Ultrathin (lt3 nm thick) silicon dioxide films are
  nitrided in order to reduce hot-electron effects
  , boron penetration and prolong the lifetime of
  the device.
• A nitride sandwiched oxide (NSO) structure was
  formed by successive NO and plasma nitridation
  steps.
• This approach reduced the leakage current to 15
  of the oxide value.

Ref10
26
ALGORITHM FOR DUAL-THRESHOLD VOLTAGE ASSIGNMENT

• Low-Vt transistors are assigned to the critical
  path in order to minimize delay .
• High-Vt transistors are assigned to non-critical
  paths to reduce leakage current
• Algorithm is for selecting the threshold voltage
  of the gates of a random logic circuit from a
  choice of two predefined voltage values.
• The goal of the selection process is to enable a
  subsequent power optimization of the circuit to
  reduce the dynamic component of the power
  dissipation.
• Since the threshold voltage of a gate is
  restricted to one of two possible choices, the
  optimization becomes a constrained 01
  programming problem.

27
COMPLEXITY OF THE PROBLEM

• Consider a circuit with N gates. There are 2N
  possible assignments of the threshold voltages of
  the gates from the set Vtl,Vth.
• To obtain the globally optimal solution, we would
  theoretically have to apply an optimal sizing
  algorithm for each of these configurations.
• In order to reduce the problem complexity, the
  algorithm is divided into two parts.
• First, we heuristically assign the threshold
  voltages of the gates to either Vtl or Vth.
• Then a power minimization algorithm is applied
  that selects the gate sizes and the supply
  voltage for minimal power operation.
• The approach reduces the complexity of the
  solution by requiring only one application of a
  global optimization algorithm as opposed to 2N
  applications.

28
ALGORITHM
Ref2

• Consider a critical path in a circuit which
  consists of high-Vt gates only.
• Arbitrarily convert one of the gates in the
  critical path to a low-Vt gate.
• The delay of this gate decreases and this creates
  a certain amount of slack in the path delay.
• Now we can afford to slow down the path by
  reducing the size of the gates in the path or
  lower the supply voltage (or both).
• This can be done such that the path still meets
  the timing deadline.
• Both of these modifications lead to a reduction
  in the dynamic power dissipation which is usually
  the dominant component of the power dissipation.

29
ALGORITM Contd

• All the gates in the circuit are initially set to
  the high threshold voltage Vth.
• The gates are then sized.
• Supply voltage Vdd is selected.
• After the power optimization step, the critical
  paths of the circuit are studied.
• A subset of the gates which are set to a
  lowthreshold voltage, is extracted.

30
CIRCUIT PARTITIONING FOR DUAL-THRESHOLD VOLTAGE

• The most significant part of the algorithm is the
  selection of the gates that are assigned a low
  threshold voltage.
• Pick the gate that would lead to the largest
  reduction in the path delay.
• Consider a path P consisting of n gates g1, g2,.
  . . , gn numbered sequentially from the primary
  input to the primary output.
• The delay of the path is TP T1 T2 .......
  Tn.
• If the threshold voltage of the ith gate is
  changed, then the delays of all the gates
  occurring after gi in the path are affected

31
Contd.

• The change in the delay of gk (k gt i), for a
  small change in the threshold voltage of gi, is
  given by
• Thus, if the delay of gi changes by Ti, then the
  change in the delay of gk is ?Tk
  (ak.ak-1ai1)?Ti
• The change in the delay of path P is then given
  as

32
SELECTION OF LOW VT GATES

• Ideally, we would like to find a gate that lowers
  the delay of many critical paths.
• Experiments indicate that the gate with the
  largest value of Ti is usually one that has a
  number of paths passing through it.
• This is due to the fact that a gate with many
  fanin or fanout nets has to drive a large
  capacitive load and hence has a large delay.
• Hence, it follows that the gate with the largest
  value of the product Ai Ti is likely to be a very
  suitable candidate.

33
EXPERIMENTAL RESULT

• The values of the high and low threshold voltages
  were set to 400 and 200 mV, respectively.
• In some instances the total power reduces by more
  than 50.
• Experiments indicate that approximately 3035 of
  the gates corresponds to a good tradeoff between
  the static and dynamic power components.

• As

34
SUMMARY

• Reducing and Optimizing the Threshold and Supply
  Voltage is the key to reduced power consumption
  and dissipation without performance degradation.
• Many different algorithms can be implemented in
  order to find the optimal values
• Nitridation improves the performance of the Gate
  Oxide
• Clock systems and a logic part consume almost the
  same power and hence reducing clock swing reduces
  power consumption
• Using Sleep Mode to switch of the clock to an
  idle part of the circuit also results in low
  power consumption

35
CONCLUSION

• Power dissipation is a barrier for the continuing
  trend of system integration on chip and high
  performance portable applications.
• Typically, the dynamic component will dominate,
  making it the primary target for power reduction.
• Reduction in power supply and threshold voltage
  can reduce power dissipation by a large margin
  although it affects performance.
• By careful design one can have low power circuits
  without affecting the performance by a large
  factor.
• FUTURE TRENDS
• Interest in System-On-a-Chip (SOC) design.
• Lithography to enable the manufacturing of
  components with smaller dimensions.
• Smaller dimensions will have smaller capacitances
  and hence reduce total power dissipation.

36
BIBLIOGRAPHY

• 1 Low-Power CMOS Digital Design by Anantha P.
  Chandrakasan, Samuel Sheng, and Robert W.
  Brodersen IEEE Journal of Solid State Circuits,
  Vol.27, No.4
• 2 Dual-threshold voltage assignment with
  transistor sizing for low power CMOS circuits by
  Pankaj Pant, Rabindra K. Roy, and Abhijit
  Chatterjee - IEEE Transactions on Very Large
  Scale Integration (VLSI) Systems, Vol. 9, No. 2
• 3 Design and Optimization of Dual-Threshold
  Circuits for Low-Voltage Low-Power Applications
  Liqiong Wei, Student Member, IEEE, Zhanping Chen,
  Student Member, IEEE, Kaushik Roy, Senior Member,
  IEEE, Mark C. Johnson, Yibin Ye, Member, IEEE,
  and Vivek K. De, Member, IEEE - IEEE Transactions
  On Very Large Scale Integration (VLSI) Systems,
  Vol. 7, No. 1
• 4 Experimental Exploration of Ultra-Low Power
  CMOS Design Space Using SOIAS Dynamic V, Control
  Technology Isabel Yang, Anthony Lochtefeld, Siva
  Narendra, Anantha Chandrakasan, Dimitri A.
  Antoniadis Massachusetts Institute of Technology,
  39-415, Cambridge, MA 021 39 - Proceedings 1997
  IEEE International SO1 Conference, Oct. 1997
• 5 Logic Design For Low-power CMOS Circuits by C.
  Piguet, CSEM Centre Suisse d'Electronque et de
  Microtechnique SA Malad2re 71,2000 Neuchatel,
  Switzerland
• 6 Low Power CMOS Design Strategies by Matthias
  Schobinger and Tobias G. Noll

37
BIBLIOGRAPHY

• 7 Low Voltage Low Power CMOS Design Techniques
  for Deep Submicron ICs by Liqiong Wei, Kaushik
  Roy, Vivek K. De
• 8 Low-Power CMOS Design through V, Control and
  Low-Swing Circuits by Takayasu Sakurai , Hiroshi
  Kawaguchi and Tadahiro Kuroda
• 9 Low-Power Digital Design by Mark Horowitz,
  Thomas Indermaur, and Ricardo Gonzalez, Center
  for Integrated Systems, Stanford University,
  Stanford, CA 94305
• 10 Nitride-sandwiched-oxide gate insulator for
  low power CMOS by D. Ishikawa, S. Sakai, K.
  Katsuyama and A. Hiraiwa
• 11 Supply and Threshold Voltage Scaling for Low
  Power CMOS by Ricardo Gonzalez, Benjamin M.
  Gordon, and Mark A. Horowitz - IEEE JOURNAL OF
  SOLID-STATE CIRCUITS, VOL. 32, NO. 8
• 12 Variable Supply-Voltage Scheme for Low-Power
  High-Speed CMOS Digital Design by Tadahiro
  Kuroda, Member, IEEE, Kojiro Suzuki, Shinji Mita,
  Tetsuya Fujita, Fumiyuki Yamane, Fumihiko Sano,
  Akihiko Chiba, Yoshinori Watanabe, Koji Matsuda,
  Takeo Maeda, Takayasu Sakurai, Member, IEEE, and
  Tohru Furuyama, Member, IEEE - IEEE Journal Of
  Solid-state Circuits, Vol. 33, No. 3
• 13 A Low-Swing Clock Double-Edge Triggered
  Flip-Flop by Chulwoo Kim, Member, IEEE, and
  Sung-Mo (Steve) Kang, Fellow, IEEE
• 14 CMOS Design Challenges to Power Wall by
  Tadahiro Kuroda
• 15 50 ActivePower Saving without Speed
  Degradation using Standby Power Reduction (SPR)
  Circuit Katsuhiro Seta, Hiroyuki Ham, Tadahiro
  Kurcda, Masakazu Kakumu, Takayasu Sakurai
• 16 On High Noise Immunity CMOS Design Scheme
  with Low Leakage Power Consumption by Mohammad
  Abbas, Makato Ikeda, Kunihiro Asada