Implementation of Precise Interrupts in Pipelined Processors

1
Implementation of Precise Interrupts in Pipelined
Processors

• James E. Smith
• Andrew R. Pleszkun

2
Outline

• Motivation for precise interrupts.
• Types of interrupts.
• What are precise interrupts?
• 5 solutions to the precise interrupt problem.
• Performance results.
• Extensions.
• Conclusions.

3
Motivation

• An interrupt may occur at any time.
• If this happens we need to be able to return to
  some point to restart execution.
• Still need to get the right answer.
• With pipelining hardware may not be in a state
  consistent with any PC value.
• This paper presents 5 solutions to this.

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Types of Interrupts

• Program interrupts.
• traps
• Errors detected while fetching and executing
  instructions.
• Illegal op-code, numerical errors, page faults
• External interrupts.
• Caused by sources outside the executing process.
• I/O interrupts, timer interrupts

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Precise Interrupts

• The saved state is consistent with sequential
  model of execution.
• Process state consists of PC, registers, and
  memory.
• Three criteria
• Previous instructions have finished.
• Later instructions are completely unexecuted.
• Interrupted instruction has finished/not started.

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In-Order Instruction Completion (1/5)

• Instructions modify state only when all previous
  instructions are known to be exception-free.
• Implemented with the result shift register.
• Insures preciseness w.r.t. registers.
• Instruction reserves all stages up to and
  including its own.
• If an exception is detected, all subsequent
  instruction are simply cancelled.

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Memory and PC Preciseness (1)

• Two methods to make memory precise.
• Force stores to wait until the result shift
  register is empty before issuing.
• Stores can wait in the load/store pipeline until
  all preceding instructions are exception free.
• To make program counter precise
• Simply include the PC with each entry in the
  result shift register.

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Problems with (1)

• Faster instructions may have to wait for slower
  ones, even if no dependencies exist between the
  two instructions.
• Faster instructions block slower instructions
  which would need later stages of the result shift
  buffer anyway.

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Reorder Buffer (2/5)

• Results of an instruction are sent to the reorder
  buffer.
• Here they wait until all preceding instructions
  have committed.
• This allows instructions to finish out of order.
• When an exception occurs, issue is stopped and no
  more instructions are executed and no register
  writes are allowed.

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Memory and PC Preciseness (2)

• Memory can be made precise in 2 ways
• Hold stores in issue register until all previous
  instructions are know to be exception free.
• Allow dummy stores in the reorder buffer.
• PC preciseness.
• Store the PC in the reorder buffer instead of the
  result shift register.
• When an exception occurs, use the PC from the ROB.

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Problems with (2)

• Already computed results must wait in the reorder
  buffer when they may be needed by other
  instructions which could otherwise execute.
• Data dependent instructions must wait until the
  result has been committed to register.

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Bypass Paths (3/5)

• Can implement bypassing, or forwarding, from the
  reorder buffer.
• Allows data in ROB to be used in place of data in
  registers.
• Dependent instructions are allowed to issue.
• Only latest entry in ROB can be used.
• Preciseness w.r.t. memory and PC do not change
  from (2).

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Problems with (3)

• Many bypass comparators are needed.
• Lots of extra circuitry is required for the
  multiple bypass check.
• Fortunately, the circuitry is conceptually simple.

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History File (4/5)

• Uses a history buffer, much like a reorder
  buffer.
• Stores register number and contents before
  change.
• Results go straight into the registers if there
  is no exception.
• On an exception the history buffer is emptied,
  resetting the registers they contain.

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Memory and PC Preciseness (4)

• The precise PC can be found at the head of the
  history buffer.
• Stores can wait in the issue register or be
  blocked in the memory pipeline.

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Future File (5/5)

• Uses two separate register files
• Architectural file - Represents sequential
  execution.
• Future file - Updated immediately upon
  instruction execution and used as the working
  file.
• When instruction reaches the head of ROB, it is
  committed to the architectural file.
• On an exception changes are brought over from the
  architectural file to the future file based on
  which instructions are still represented in the
  ROB.
• Preciseness maintained just as with (4).

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Performance Measurements

• Cray-1S simulation system was used.
• Workload was the first 14 Lawrence Livermore
  Loops.
• (3), (4), and (5) all performed the same, so are
  represented simply as (3).
• Number of buffer entries was varied to assess
  effect on performance.

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Results Tables
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Extensions

• These methods can be modified to provide support
  for the following extensions
• Handling other state values.
• Virtual memory.
• Cache-Memory.
• Linear pipeline structures.

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Conclusion

• This paper presented five methods to provide
  precise interrupts.
• Through simulation, these methods were shown to
  reduce performance by as little as 3.
• Varying implementation costs may make a slower
  but cheaper method more appropriate.