A few notes for your design

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A few notes for your design

• Finger and multiplier in schematic design
• Parametric analysis
• Monte-Carlo analysis

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Multi-Fingered Transistors
One finger
Two fingers (folded)
Less diffusion capacitance
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Digital Integrated CircuitsA Design Perspective
Jan M. Rabaey Anantha Chandrakasan Borivoje
Nikolic
Designing CombinationalLogic Circuits
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Multistage Networks
Stage effort hi gi fi Path electrical effort
F Cout / Cin Path logical effort G
g1g2gN Path effort H GF Path delay D Sdi
Spi Shi
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Optimum Effort per Stage
When each stage bears the same effort
Stage efforts g1f1 g2f2 gNfN
Effective fanout of each stage
Minimum path delay
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Example Optimize Path
g1 1
g4 1
g2 5/3
g3 5/3
Effective fanout, F 5 G 25/9 H GF125/9
13.9 h 1.93 f1h/g1.93 f21.933/51.16 f31
.16 f41.93 (f1 effective fanout for the first
stage) a f1g1/g21.16 (of minimum-size
3-input NAND gate) (ag2f1g11) b
f1f2g1/g3 1.34 (of minimum-size 2-input NOR
gate) (bg3f2g2a) c f1f2f3g1/g4
2.59 (of minimum-size inverter)
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Add Branching Effort
Branching effort
A parameter used to account for how much sizing
is attributed to the critical path
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Multistage Networks
Stage effort hi gi fi Path electrical effort
F Cout / Cin Path logical effort G
g1g2gN Branching effort B b1b2bN Path
effort H GFB Path delay D Sdi Spi Shi
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Example 8-input AND
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Optimal Number of Stages
For a given load, and given input capacitance of
the first gate Find optimal number of stages and
optimal sizing
Substitute best stage effort
best number of stages N log4H
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Method of Logical Effort

• Compute the path effort H GFB
• Find the best number of stages N log4H
• Compute the stage effort h H1/N
• Sketch the path with this number of stages
• Work from either end, find sizes
• Reference Sutherland, Sproull, Harris, Logical
  Effort, Morgan-Kaufmann, 1999.

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Summary
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Power consumption of static gates

• It is a strong function of transistor sizes
  (which affects physical capacitance), input and
  output rise and fall time, device thresholds,
  temperature and switching activity.
• Switching activity is a strong function of logic
  function to be implemented (nature of the gate),
  also input signal statistics such as inter-signal
  dependency.
• Estimate switching activity for the overall chip
  is a very difficult task.
• eg. For NOR gate, PA, PB the probabilities that
  input A and B stays at 1. Transition probability
  is then
• ?0-gt1 1-(1-PA)(1-PB) (1-PA)(1-PB)

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Complementary MOS Properties

• Full rail-to-rail swing high noise margins
• Logic levels not dependent upon the relative
  device sizes ratioless
• Always a path to Vdd or Gnd in steady state low
  output impedance
• Extremely high input resistance nearly zero
  steady-state input current
• No direct path steady state between power and
  ground no static power dissipation
• Propagation delay as function of load capacitance
  and resistance of transistors

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Summary Static Complementary Gates

• Static CMOS Complementary Gates is highly
  robust, scalable and easy to be designed.
• One possible drawback is 2N number of
  transistors to implement an N-input logic
  function.
• Another drawback is that parasitic capacitance
  is significant (driving two devices for fan-in
  and fan-out)
• This opens the door for alternative logic design
  styles (either simpler or faster)

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Ratioed Logic
Static/dynamic Ratioed/ratioless Complementary/non
-complementary
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Ratioed Logic
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Ratioed Logic
In ratioed logic, the entire PUN is replaced with
a single unconditional load device that pulls up
the output for logic 1
Not zero!!
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Active Loads
Voltage swing now depend on the ratio of
NMOS/PMOS (in contrast to ratioless complementary
logic), so named ratioed
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Pseudo-NMOS
Linear region
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Pseudo-NMOS inverter VTC
Fix W/L2 for NMOS transistor
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Ratioed logic with better loads

• It is possible to create a ratioed logic that
  completely eliminates static currents and
  provides rail-to-rail swing
• Such logic combines two concepts differential
  logic and positive feedback (make sure that load
  device is turned off when not needed)
• An example of such a logic family is called DCVSL

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Improved Loads
Both the logic and its inverse are simultaneously
implemented
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DCVSL Example
It is possible to share transistors among the two
pull-down networks. DCVSL gives rail-to-rail
swing and eliminates static power dissipation.
But short-circuit power may be a problem.
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DCVSL Transient Response
Delay In-gtout 197ps In-gtout 321ps VS 200ps for
Static MOS
Still ratioed since sizing of PMOS/NMOS critical
to function Short-circuit path due to
simultaneous on of PMOS/NMOS
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Pass-TransistorLogic
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Pass-Transistor Logic
Allow inputs to drive source/drain terminals as
well as gate terminals
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Example AND Gate
NMOS only
Is B redundant?
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NMOS-Only Logic
Unfortunately, NMOS passes strong 0 but weak 1
(the situation is even worsened by body effect)
Avoid cascading multiple pass-logic without
buffering!!!
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NMOS-only Switch
V
V
does not pull up to 2.5V, but 2.5V -
TN
B
Though smaller voltage swing causes smaller
dynamic power consumption, threshold voltage loss
causes
static power consumption of following inverters