Ch 8 Interfacing Processors and Peripherals

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Ch 8 Interfacing Processors and Peripherals

• 8.1 Introduction
• 8.2 I/O Performance Measures
• 8.3 Types and Characteristics of I/O Devices
• 8.4 Buses
• 8.5 Interfacing I/O Devices to Memory, Processor
  and OS

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8.1 Introduction
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8.1 IntroductionImpact of I/O on System
Performance

• Assume the following
• Benchmark executes in 100 seconds of elapsed
  time
• 90 seconds are CPU time
• rest I/O time
• If CPU time improves 50 per year for 5 years,
  but I/O stays the same, how much faster will the
  benchmark run at the end of 5 years?
• Elapsed time CPU time I/O time
• 100 90 seconds I/O time, thus I/O time 10
  seconds

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8.1 IntroductionImpact of I/O on System
Performance Continued
CPU improvement 90/12 7.5 fold Elapsed time
improvement 100/22 4.5 fold
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8.1 IntroductionAssessing I/O Performance

• I/O bandwidth
• How much data can transfer at any given time?
• How many I/O operations can we perform per unit
  of time?
• Response time (elapsed time)
• key to single-user PC's and workstations
• Often times one measure is more important than
  the other
• Payroll throughput
• Most times however, both are
• ATM

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8.2 I/O Performance Measures

• Transfer rate quoted in MB/sec
• MB is base 10, not 2
• 1 MB 106 1,000,000
• Supercomputer I/O Benchmarks
• Data throughput
• Transaction Processing I/O Benchmarks
• Response time and throughput
• I/O rate (disk accessed per second) rather than
  data rate (bytes per second)

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8.2 I/O Performance MeasuresContinued

• File System I/O Benchmarks
• reads
• writes
• read/writes

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8.3 Types and Characteristics of I/O Devices

• Three characteristics
• Behavior Input (read once), output (write only,
  cannot be read), or storage (can be reread and
  usually rewritten)
• Partner Either a human or a machine on other
  end reading data on output or writing data on
  input
• Data rate The peak rate of transfer between I/O
  device and main memory or processor

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8.3 Types and Characteristics of I/O
DevicesContinued
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8.3 Types and Characteristics of I/O DevicesMouse

• Two forms
• generates pulses when moved (LED and detector)
• increments and decrements counters
• OS polls mouse status frequently

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8.3 Types and Characteristics of I/O
DevicesMagnetic Disks

• Two types
• floppy disks
• hard disks
• HD advantages over FD
• larger because its rigid (metal or glass)
• higher density
• higher data rate due to higher spin rate
• can have more than one platter

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8.3 Types and Characteristics of I/O
DevicesMagnetic Disks Continued

• 1-15 platters
• recordable on both sides
• 3600-7200 rpm
• dia 1-8"
• 1000-5000 tracks/surface
• 64-200 sectors/track
• block access
• 1 block 512 bytes
• varying of sectors/track
• bit spacing kept constant
• cylinder all tracks under the heads

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8.3 Types and Characteristics of I/O
DevicesAccessing Data

• Seek - position head over the proper track
• seek time 8 to 20 ms
• Rotational latency or rotational delay time for
  proper sector to rotate under the head
• ½ rotation on average
• 0.5 rev/3600 rpm/60 sec/min 0.0083 sec 8.3 ms
• 0.5 rev/7200 rpm/60 s/m 0.0042 sec 4.2 ms
• Transfer time time to transfer a block of bits
• 2 to 15 MB/sec
• Controller time time overhead imposed by disk
  controller

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8.3 Types and Characteristics of I/O
DevicesExample
1 sector 512 bytes rotation 5400
rpm average seek time 12 ms transfer rate 5
MB/sec controller overhead 2 ms Assume no
waiting time. What is the average time to read or
write one sector?
12 ms (0.5/(5400/60))1000 ms 512/5/1000 ms
2 ms 12 ms 5.6 ms 0.1 ms 2 ms 19.7 ms
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8.3 Types and Characteristics of I/O DevicesDisk
Densities and Size
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8.3 Types and Characteristics of I/O
DevicesNetworks

• Key characteristics
• Distance 0.01 to 10,000 km
• Speed 0.001 MB/sec to 100 MB/sec
• Topology Bus, ring, star, tree
• Shared lines None (point-to-point) or shared
  (multidrop)
• RS232 standard
• 0.3 19.2 kbs
• point-to-point, star network
• terminals are 10 to 100 m from computer

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8.3 Types and Characteristics of I/O
DevicesNetworks Continued

• LAN
• Ethernet most likely
• 10 Mbs, 100 Mbs or 1Gbs one wire bus w/out
  central control
• packets (64 bytes to 1518 bytes) are transmitted
  over the bus
• only one sender can use the bus at a time, so
  limited bandwidth
• switching helps reduce the number of hosts on
  each Ethernet segment
• Long-haul networks
• 10 to 10,000 km
• ARPANET (point-to-point, 56 kbs)
• each packet was routed differently and assembled
  at the host
• TCP/IP, guarantee packet delivery w/no
  errors/resolves addressing between two hosts

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8.3 Types and Characteristics of I/O
DevicesTCP/IP Packets
IP header
Destination
Source
IP Data
Sequence number (length)
0-65,516 bytes
TCP data
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8.4 Buses

• Allows memory and I/O devices to communicate with
  the processor
• Uses two sets of wires, for control and data
• Advantages
• versatility (can add devices to it easily)
• low cost (bus shared in different ways)
• Disadvantage
• communication bottleneck

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8.4 BusesBus Transaction Output (mem to I/O)
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8.4 BusesBus Transaction Input (I/O to mem)
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8.4 BusesTypes of Buses

• Processor-memory bus
• short, high speed matched to the memory system
• usually proprietary
• I/O bus
• lengthy
• connecting multiple different devices
• connect to memory indirectly through
  processor-memory or backplane bus
• backplane bus
• allows processor, memory and I/O devices to
  coexist on same bus

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8.4 BusesTypes of Buses Continued
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8.4 BusesSynchronous Buses

• Synchronous
• clock in control lines
• fixed protocol for communicating that is relative
  to the clock
• usually processor-memory buses
• Disadvantages
• all devices must run at same clock rate
• cannot be long if they are fast (clock skew
  problems)

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8.4 BusesAsynchronous Buses

• Asynchronous
• not clocked
• accommodates a wide variety of devices
• can be lengthier (no clock skew problem)
• uses a handshaking protocol
• additional control lines needed for handshaking
• Assume the following control lines
• ReadReq read memory request
• DataRdy data is ready on the data lines
• Ack acknowledge the ReadReq, DataRdy signal of
  the other party

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8.4 BusesAsynchronous Handshaking

• Read a word from memory and write to I/O device

R
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a
d
R
e
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valid data
D
a
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a
asserted by I/O
asserted by memory
A
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k
D
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a
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1. Memory sees the ReadReq, reads the data from
data lines and sets AcK
Protocol steps begin once I/O device signals a
request by raising ReadReq and putting the
address on the data lines.
2. I/O sees the Ack as high and releases the
ReadReq and data lines
3. Memory sees ReadReq as low, drops the Ack line
to acknowledge the ReadReq signal
4. Starts when memory has data ready. Puts data
in data lines and raises DataRdy
5. I/O sees DataRdy, reads the data from the bus
and raises the Ack
6. Memory sees Ack, drops DataRdy and releases
the data lines
7. I/O sees DataRdy low, drops the Ack to
indicate transmission is complete
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8.4 BusesSynchronous v. Asynchronous Performance

• Synchronous bus clock cycle time 50 ns
• Bus transmission 1 clock cycle or 50 ns
• Asynchronous bus 40 ns per handshake
• Data lines 32 bits wide
• DRAM access 200 ns
• Find the bandwidth (MBS) for each bus when
  performing 1-word reads from memory

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8.4 BusesSynchronous v. Asynchronous Performance
Continued
Synchronous bus Time send address to memory
read memory send data to IO Time 50 ns 200
ns 50 ns 300 ns bandwidth 4 Bytes/300 ns
1.33 MBS
Asynchronous bus Time step 1 max(steps 2-4,
memory read) steps 5-7 Time 40 ns max(120,
200) ns 3 x 40 ns Time 40 ns 200 ns 120
ns 360 ns bandwidth 4B/360ns 1.11 MBS
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8.4 BusesIncreasing the Bus Bandwidth

• Additional factors affecting bandwidth
• Data bus width increasing the data width,
  transfers of multiple words requires fewer bus
  cycles
• Separate v. multiplexed address and data lines
  separate address lines makes writes faster, since
  address and data can be made available in one bus
  cycle
• Block transfers transferring multiple words in
  back-to-back bus cycles w/out interruption,
  reduces block transfer time

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8.4 BusesObtaining Access to the Bus

• Many devices are vying for a bus's attention
• We must have a mechanism in place to allow proper
  access to the bus by all devices requiring such
  access
• Introduce bus masters to control access to the
  bus. It initiates and controls all bus requests
• The processor is always a bus master, since it
  must request memory accesses
• Memory is a slave, since it does not originate
  requests, just responds to them

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8.4 BusesSingle Bus Master

• The CPU acts as the single bus master. Not a very
  efficient use of the CPU

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8.4 Buses Bus Arbitration

• Deciding which bus master gets to use the bus
• Bus master requests and is granted bus access
• Devices have bus priority, and device with
  highest priority gets served first
• Devices should never be blocked from accessing
  the bus, even if they have a low priority

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8.4 Buses Bus Arbitration Continued

• Four arbitration schemes
• Daisy chain arbitration
• simple
• bus grant line runs through all devices
• high-priority device may intercept low-priority
  device
• fairness is not guaranteed
• grant line limits bus speed

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8.4 Buses Bus Arbitration Continued

• Centralized, parallel arbitration
• multiple request lines
• devices request bus independently
• centralized arbiter chooses device and makes them
  bus master
• requires centralized arbiter (possible
  bottleneck)
• used by PCI
• Distributed arbitration by self-selection
• multiple request lines
• devices requesting access, determine who gets
  access
• devices examine priority and highest priority
  device gets access
• more request lines
• used by NuBus on Apple IIs

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8.4 Buses Bus Arbitration Continued

• Distributed arbitration by collision detection
• devices request bus independently
• multiple simultaneous requests result in a
  collision
• scheme resolves collision and a device is
  selected
• used by Ethernets

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8.5 Interfacing I/O Devices to Memory, Processor
and OS

• Question What is the role of the operating
  system?
• grants a user's program access to the portions of
  an I/O device to which the user has rights
• provides routines for performing low-level device
  operations
• handles the interrupts generated by I/O devices,
  as well as program exceptions
• tries to provide equitable access to the I/O
  resources, and schedule accessed in order to
  enhance system throughput

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8.5 Interfacing I/O Devices to Memory, Processor
and OS

• Three types of communication are required for OS
  to carry out its role
• The OS must be able to give commands to the I/O
  devices (read, write, seek ...)
• The device must be able to notify the OS when
  task is complete or error has occurred
• Data must be transferred between an I/O device
  and memory

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8.5 Interfacing I/O Devices to Memory, Processor
and OS

• Question How is the user I/O request transformed
  into a device command and communicated to the
  device?
• Processor must address the device and provide one
  or more command words
• Two methods to address the device
• memory-mapped I/O (portions of memory are
  assigned to I/O devices)
• special I/O instructions
• Processor polls the device to see if done or in
  error
• I/O device sends an interrupt to notify OS that
  attention is required

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8.5 Interfacing I/O Devices to Memory, Processor
and OS

• Question How is data actually transferred to or
  from a memory location?
• Two methods can be implemented
• work best with lower bandwidth devices
• both polling and interrupt-driven transfers put
  the burden of the transfer on the processor