Verification Technologies

1
Formal Specification Using Sugar 2.0
Cindy Eisner
September 2002
Verification Technologies IBM Haifa Labs

2
Overview

• Declarative language for specification of
  hardware
• Concise, intuitive formalism to reason about
  behavior over time
• Combines
• temporal logic and
• regular expressions
• under a convenient layer of user-friendly
  syntactic sugar
• Sugar is used as
• easy-to-read but precise specification
• input to formal verification
• source of automatically generated checkers for
  simulation

3
History

• 1994
• Syntactic sugaring of CTL for RuleBase model
  checker
• 1995
• Addition of regular expressions
• 1997
• Automatic generation of simulation monitors
• ________________________________________________
• ________________________________________________
• 2001
• Move to linear (LTL-based) semantics
• 2002
• Selected by Accellera for IEEE standardization

Sugar 1.0
Sugar 2.0
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Track Record (Sugar 1.0)

• IBM products
• Main Frame line (S/390)
• Midrange line (AS/400)
• Workstation line (RS/6000)
• PC line (Netfinity)
• Super Computers (ASCI)
• ASIC/OEM business
• External licensees
• University program

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Sugar 2.0 - The Language
Modeling
Verification
Temporal
Boolean
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The Temporal Layer
Modeling
Verification
Temporal
Boolean
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Simple Invariants

• If data_en is de-asserted, then data_out must be
  de-asserted as well.
• always (!data_en -gt !data_out)
• Signals ena and enb are never asserted
  simultaneously.
• never (ena enb)

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Relations Over Time

• If req is asserted, then ack must be asserted the
  following cycle.
• always (req -gt next ack)
• If req is asserted, ack must be asserted four
  cycles later.
• always (req -gt next4 ack)
• If req is asserted, ack must be asserted some
  time in the future.
• always (req -gt eventually! ack)

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Relations Over Time, cont.

• Whenever a high priority request is received, the
  next grant should be to a high priority
  requester.
• always (hi_pri_req -gt next_event(grant)(dsthi_pri
  ))
• Whenever a request is issued, signal last_ready
  must be asserted on the fourth assertion of
  signal ready.
• always (req -gt next_event(ready)4(last_ready))

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Regular Expressions

• If req is asserted, then eventually we must see
  an ack that is not aborted.
• always (req -gt eventually! ack !abortin)

req
ack
abortin
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Regular Expressions, cont.

• A sequence of req followed by ack should be
  followed by a full data transaction an
  assertion of start_trans, followed by eight
  consecutive data transfers, followed by the
  assertion of end_trans.
• always reqack gt start_transdata8end_tra
  ns

req
ack
starttrans
data
endtrans
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Regular Expressions, cont.

• A sequence of req followed by ack should be
  followed by a full data transaction an
  assertion of start_trans, followed by eight (not
  necessarily consecutive) data transfers, followed
  by the assertion of end_trans.
• always reqack gt start_transdata8end_tra
  ns

req
ack
starttrans
data
endtrans
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Hardware clocks

• Consider only cycles in which the clock ticks
• always (req -gt next4 ack) _at_ (clk)

clk
req
ack
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Hardware clocks, cont.

• Support for multiply-clocked designs
• always (p -gt next (q_at_clkq))_at_clkp

i
p
clkp
q
clkq
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Hardware resets

• Synchronous reset
• always
• (reqack -gt startdata8end abort reset)
  _at_ (clk)
• Asynchronous reset
• always
• ((reqack -gt startdata8end) _at_ (clk))
  abort reset)
• 
  

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Standardization Status

• Endorsed publicly by many EDA vendors, including
• Cadence
• Mentor Graphics
• Co-Design Automation
• 0-In Design Automation
• Novas Software
• Accellera recommendation will be submitted to
  IEEE by year end 2002

• Real Intent
• TransEDA
• Verplex
• Veritable
• Structured Design Verification

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Tool Support
Company
Tool
Function
IBM
RuleBase
Model Checker
IBM
FoCs
Generator of Simulation Monitors
NoBug Consulting
Specification Compiler
S2E
TransEDA
Dynamic Property Checker
VN-Property DX
Cadence
Verification Cockpit
Dynamic Static Property Checking
Avery
TestWizard
Testbench Automation Tool
TNI/Valiosys
Model Checker
imPROVE-HDL
Esterel
Full-flow solution for design verification
Esterel Suite
_at_HDL
_at_Verifier
Model Checker
0-In
CheckerWare
Library of Protocol Checkers
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Sugar home page

• More information available on the Sugar home page
  at
• www.haifa.il.ibm.com/projects/verification/sugar/i
  ndex.html
• Complete definition
• Tutorial
• Sugar parser
• more