ArrayBased Architecture for Molecular Electronics

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Array-Based Architecture for Molecular Electronics

• André DeHon
• andre_at_cs.caltech.edu
• Monday, July 8, 2002

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Previously

• VLSI end of roadmap
• Brick walls
• Physical limits
• Chemical/bottom-up assembly
• Cost landscape affects organization

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Computing?

• Problem Can we build electronic systems
  (computing devices) from chemical
  nano-technology?
• Organize into useful connectivity?
• Provide signal restoration?
• Personalize/Engineer to perform specific
  computation?
• Accommodate defects?

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Architecture Goal

• This talk
• Starting with molecular-scale building blocks
• Show how to build universal, programmable
  computing array.

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Outline

• Review Components
• Introduce nanoFETs
• Restoring Logic Style
• Digital abstraction
• Bootstrap Programming
• Routing
• Defect Tolerance
• Summary

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Wires
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Devices
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Unique Characteristics

• Can only build very regular structures at
  nanoscale
• Arrays of crossed tubes / wires
• Will have many defects
• Can store state of switch in wire crossing
• Contrast with VLSI where switch gtgt wire xing
• Switching occurs at tube/wire crossing
• Not at substratelong term 3D opportunity

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Strategy
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Strategy

• Arrays of FETs for gain
• FET decode for bootstrap program
• PLA logic in arrays
• Overlapping wires for interconnect

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Logic Discipline
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Diode Logic

• Arise directly from touching NW/NTs
• Passive logic
• Non-restoring

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PMOS-like Restoring FET Logic

• Use FET connections to build restoring gates
• Static load
• Like NMOS (PMOS)

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PMOS-like Logic
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Operating Point
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Programmed FET Arrays
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Interfacing and Programming

• Micro?nanoscale

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Personalization

• How do we program/customize for a specific
  function?
• Differentiate homogeneous arrays?
• W/ PLA
• Reduce to programming connections
• Which crosspoints connected/unconnected

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Personalization

• Treat array core like memory
• Program up desired connections
• Achieved by applying voltage across junction

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FET Decoders

• FETs also ideal for decoding/drive at nano-micro
  interface

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Program Decoder

• Will need to program the decoder
• Different scheme in fabrication
• Imprinting/stamping
• or Kuekes/HP showed random decoder

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Operating Array

• Decoders allow program array
• OR, NOR
• Isolatable
• Dual role of loads during operation
• Output used directly by consumer

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Assembly

• Overlapping NW/NT between arrays provide
  interconnect
• NOR only sufficient
• Alternate
• Programmable (non-restoring) OR
• followed by fixed (restoring) NOR

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Routing

• X-Y, mesh routing with appropriate tile overlap

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Defect Tolerance
All components (PLA, routing) interchangeable All
ows local programming around faults
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Robust Addressing

• If address lines may fail,
• Dont want to use dense (log(N)) encoding
• Losing one address line
• Cuts number of accessible lines in half!

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Robust Addressing

• Consider 2-hot codes
• Each tube addressed by two ones
• There are A(A-1) codes of length A
• Only lose A codes per fault or (sqrt(N)) tubes

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Crossbar size?
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Crossbar Size

• Larger crossbar
• Amortize out microscale addressing overhead
• Smaller crossbars
• Shorter wires
• Less capacitance ? faster, less energy
• Less likely to fail
• More efficient for logic

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Area Model

• Aside (NA(N)) Wmolecular A(N)Wcmos
• 2-hot codes
• A(N)?sqrt(2N)?1
• S(Aside)2

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Area vs. Array Size
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Simple Defect Model

• Primary failure is contacts at end of tubes Pc
• Some failure proportional to length of tube
• Breaks in tube, bad junction Pj
• Good tube requires no failures
• Ptube (1-Pc)2(1-Pj)N

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Yield vs. Array Size
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Net Area vs. Array Size
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Crossbar Size

• Based on
• Relative size of structures
• Micro vs. nano
• Overhead of current model
• Current defect rate estimates
• Modest arrays appropriate
• 512 NT/NW per side
• A(512)11
• Aside 1190nm (51211)10nm
• 45-65 yield ?
• 400-800 nm2/crosspoint

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Caveat

• Still need to examine logical efficiency
• Yielded gates
• How efficient gates in large PLA
• Wiring
• Fraction of wires for routing

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Summary

• Universal, Programmable Architecture
• Built entirely from large arrays of crossed
  NT/NWs
• Provides restoration and inversion entirely at
  nanoscale
• Support nanoscale bootstrap programming
• Designed to tolerate defective components