Instruction Set Architecture

1
Instruction Set Architecture

• The portion of the machine visible to the
  programmer
• Issues
• Internal storage model
• Addressing modes
• Operations
• Operands
• Encoding
• Compilation Issues

2
Internal Storage Model

• Memory- Memory (Add C, A, B)

3
Internal Storage Model

• Most post 1980 architectures use a load store
  architecture
• Main reasons
• registers faster than memory
• Compilers can utilise registers more effectively
  than other models
• Variables can be held in registers
• Instruction set can use 2 or 3 operand format

4
Memory Addressing

• How
• memory addresses interpreted
• memory addresses are specified
• Interpretation
• Size (byte, half word, word)
• Ordering (Big Endian, Little Endian)
• Alignment (Word)

5
Memory Addressing (Addressing modes)

• How an address is specified
• Modes included on machines
• Register (e.g. Add R4, R3)
• Immediate (e.g. Add R4, 3)
• Displacement (e.g. Add R4, 100(R1))
• Absolute (Add R4, (1000))
• Memory Indirect (Add R4 _at_(R3))
• Autoincrement (Add R4, (R1))
• Autodecrement (Add R4, -(R1))

6
Memory Addressing

• Use of addressing Modes
• register accounts for 50 (not counted below)

1
7
Displacement

• What is the range of displacements used

8
Immmediate
9
Immediate
10
Operations in the Instruction Set

• Can be classified into the following types
• Arithmetic and logical
• Data transfer
• Control
• System

11
Top 10 instructions on 8086

• Averaged over 5 SPECin92 programs

12
Instructions for Control Flow

• Four types
• Conditional Branches
• Jumps
• Procedure Calls
• Procedure returns
• Destination address must always be supplied. Can
  be
• specified explicitly
• indirect jumps (procedure return)

13
Branch Distance
14
PC relative Branching

• Target often close to the branch instruction
• Destination is obtained by adding a displacement
  to the PC
• Requires fewer bits to encode instruction
• helps make code position independent

15
Specifying Branch Condition

• Most branches are equalityinequality tests or
  comparisons with zero

16
Type and Size of Operands

• Two main alternatives
• operand types specified in opcode(e.g. add,
  addb, addf)
• data annotated with tags(very rare)

17
Encoding the Instruction Set

• Representation affects
• size of compiled program
• implementation of CPU
• Architect must balance
• the desire to have as many registers and
  addressing modes as possible
• the impact of the size of register and addressing
  mode fields

18
Variations in Instruction decoding

• VIARABLE (e.g. VAX, 68000)
• Better code density
• FIXED (e.g. MIPS and PowerPC)
• Simpler hardware

...
Opcode
Add spec 1
Add field 1
Add spec n
Add field n
Opcode
Result
Operand 1
Operand 2
19
Example 1 A Registerless processor

• L1 Cache and registers about same speed
• no need for registers
• An fixed length instruction set with 3 operand
  format is proposed
• Simulations show that the number of instructions
  execution is about half of a load store
  architecture