Development of a Reusable Cryptographic Core Module

1
Development of a Reusable Cryptographic Core
Module

• Sponsor Booz Allen Hamilton
• Mentors Joe Kish, Brian Russell, and Mike Hom
• Group 5 Week 8
• Group Members Ahmed Arif, Amy Skinner

2
Agenda

• Gantt Chart
• Progress
• Block diagram design and implementation (Ahmed)
• Explanation of AES (Amy)
• Plan For Next Week

3
Gantt Chart
4
Explanation of AES

• Works with 128 bit block and key length
• Creates a 4x4 array of inputted bytes, the
  state
• Uses binary operations to encrypt
• We will use two hexadecimal numbers to represent
  Bytes
• (i.e. 1100 0010 B2)

http//www.quadibloc.com/crypto/co040401.htm
5
AES The Breakdown

• Four different operations (diagram uses older
  nomenclature)
• AddRoundKey
• SubBytes
• ShiftRows
• MixColumns
• 10 rounds

http//ece.wpi.edu/kaps/ece578/chapter4.pdf
6
AES AddRoundKey

• The round keys are found through the Round Key
  Expansion routine
• Generates 20 words
• A word is XORed with a column in the 4x4 matrix
  and the result is the new state

AES Federal Information Processing Standards
Publication 197
7
AES - SubBytes

• SubBytes takes the original byte and replaces
  them with the one found in the table
• 13 (0001 0011) is replaces with 7d
• The main nonlinear element in AES

AES Federal Information Processing Standards
Publication 197
8
AES - ShiftRows

• ShiftRows simply shifts each row by a differing
  amount
• Row0 is shifted the the left by zero
• Row1 is shifted to the left 1 byte
• Etc

AES Federal Information Processing Standards
Publication 197
9
AES - MixColumns

• MixColumns switches the column locations
• Based on a scaled XOR operation
• S0(02S0)XOR (03S1) XOR S2 XOR S3
• indicates matrix multiplication

AES Federal Information Processing Standards
Publication 197
10
The FPGA Mapping

• The XUP Virtex-II Pro Development System is
  powered from a 5V regulated power supply.
• On-board switching power supplies generate 3.3V,
  2.5V, and 1.5V for the FPGA,
• Internal Components
• Multi-Gigabit Transceivers
• Help keep integrity of high frequency signals
• System RAM
• capacity of 2 GB or less in either 64-bit or
  72-bit organizations.
• Ethernet Interface
• supports both 100BASE-TX and 10BASE-T
  applications
• Serial Ports
• A total of four LEDs are provided for
  user-defined purposes
• USB 2

http//www.digilentinc.com/Data/Products/XUPV2P/XU
PV2P_User_Guide.pdf
11
Plan For Next Week

• Finalize the Simulink block diagram and
  implementation on FPGA
• Research more applications for the crypto-module