OUTLINE

1
Lecture 25

• OUTLINE
• Logic functions
• NMOS logic gates
• The CMOS inverter
• The CMOS inverter (contd)
• CMOS logic gates
• Reading
• Text Chap. 7-7.5

2
Logic Functions, Symbols, Notation
TRUTH NAME SYMBOL NOTATION TABLE
F A
F
A
NOT
A
F AB
F
OR
B
A
F AB
F
AND
B
3
Logic Functions, Symbols, Notation 2
A
F AB
F
NOR
B
A
F AB
F
NAND
B
A
F A B
F
XOR (exclusive OR)
B
4
Fan in/Fan out

• Complex digital operations are formed with a
  variety of gates interconnected to yield the
  desired logic function.
• Sometimes a number of inputs are connected to one
  gate input and output of a gate may be connected
  to a number of gates.
• Fan-in the maximum number of logic gates that
  can be connected at the input of a gate without
  altering its performance.
• Fan-out the maximum number of logic gates that
  can be connected to the output of a gate without
  altering its performance.
• Typical fan-in and fan-out numbers are 3.

5
Inverter NOT Gate
Vout
Vin
Ideal Transfer Characteristics
Vout
Vin
V/2
V
6
NMOS Resistor Pull-Up
Voltage-Transfer Characteristic
Circuit
vOUT
VDD
F
A
iD
vIN
0
VT
VDD
vDS
0
7
Disadvantages of NMOS Logic Gates

• Large values of RD are required in order to
• achieve a low value of VOL
• keep power consumption low
• Large resistors are needed, but these take up a
  lot of space.
• One solution is to replace the resistor with an
  NMOSFET that is always on.

8
The CMOS Inverter Intuitive Perspective
CIRCUIT
SWITCH MODELS
VDD
VDD
Rp
VOUT
VOUT
VOL 0 V
VOH VDD
Rn
Low static power consumption, since one MOSFET is
always off in steady state
VIN VDD
VIN 0 V
9
CMOS Inverter Voltage Transfer Characteristic
N sat P sat
VOUT
N off P lin
C
VDD
N sat P lin
B
D
E
A
N lin P sat
N lin P off
0
VIN
VDD
0
10
CMOS Inverter Load-Line Analysis
VGSpVIN-VDD
VIN VDD VGSp
VDSpVOUT-VDD
VOUT VDD VDSp
IDn-IDp
IDn-IDp
VIN 0 V
VIN VDD
increasing VIN
VOUTVDSn
0
VDD
0
11
CMOS Inverter Load-Line Analysis Region A
VGSpVIN-VDD
VIN ? VTn
VDSpVOUT-VDD
IDn-IDp
IDn-IDp
VOUTVDSn
0
VDD
0
12
CMOS Inverter Load-Line Analysis Region B
VGSpVIN-VDD
VDD/2 gt VIN gt VTn
VDSpVOUT-VDD
IDn-IDp
IDn-IDp
VOUTVDSn
0
VDD
0
13
CMOS Inverter Load-Line Analysis Region D
VGSpVIN-VDD
VDD VTp gt VIN gt VDD/2
VDSpVOUT-VDD
IDn-IDp
IDn-IDp
VOUTVDSn
0
VDD
0
14
CMOS Inverter Load-Line Analysis Region E
VGSpVIN-VDD
VIN gt VDD VTp
VDSpVOUT-VDD
IDn-IDp
IDn-IDp
VOUTVDSn
0
VDD
0
15
Features of CMOS Digital Circuits

• The output is always connected to VDD or GND in
  steady state
• Full logic swing large noise margins
• Logic levels are not dependent upon the relative
  sizes of the devices (ratioless)
• There is no direct path between VDD and GND in
  steady state
• no static power dissipation

16
The CMOS Inverter Current Flow during Switching
N sat P sat
VOUT
N off P lin
C
V
DD
VDD
S
G
N sat P lin
D
VOUT
VIN
B
D
E
A
D
N lin P sat
G
S
N lin P off
0
VIN
VDD
0
17
Power Dissipation due to Direct-Path Current
VDD
V
DD
vIN
S
G
0
D
i
vOUT
vIN
D
G
i
S
time
18
NMOS NAND Gate

• Output is low only if both inputs are high

VDD
RD
F
A
Truth Table
B
19
NMOS NOR Gate

• Output is low if either input is high

VDD
RD
F
A
B
Truth Table
20
N-Channel MOSFET Operation
An NMOSFET is a closed switch when the input is
high
A
B
A
B
Y
Y
X
X
Y X if A and B
Y X if A or B
NMOSFETs pass a strong 0 but a weak 1
21
P-Channel MOSFET Operation
A PMOSFET is a closed switch when the input is low
A
B
A
B
Y
Y
X
X
Y X if A and B (A B)
Y X if A or B (AB)
PMOSFETs pass a strong 1 but a weak 0
22
Pull-Down and Pull-Up Devices

• In CMOS logic gates, NMOSFETs are used to connect
  the output to GND, whereas PMOSFETs are used to
  connect the output to VDD.
• An NMOSFET functions as a pull-down device when
  it is turned on (gate voltage VDD)
• A PMOSFET functions as a pull-up device when it
  is turned on (gate voltage GND)

VDD
A1 A2 AN
Pull-up network
PMOSFETs only
input signals

F(A1, A2, , AN)
A1 A2 AN
Pull-down network
NMOSFETs only

23
CMOS NAND Gate
VDD
A
B
F
A
B
24
CMOS NOR Gate
VDD
A
B
F
A
B
25
CMOS Pass Gate
A
Y
Y X if A
X
A