CoE EE 00142 Computer Organization Set 6 MIPS Assembly Language Programming

1
CoE - EE 00142Computer OrganizationSet 6 MIPS
Assembly Language Programming

• Ron Hoelzeman

2
Instruction Set
3
MIPS Instructions

• More primitive than higher level languages e.g.,
  no sophisticated control flow
• Very restrictive e.g., MIPS Arithmetic
  InstructionsMIPS instruction set architecture
• similar to other architectures developed since
  the 1980's
• used by NEC, Nintendo, Silicon Graphics, Sony

4
Overview of MIPS

• Simple instructions all 32 bits wide
• Very structured, no unnecessary baggage
• Only three instruction formats

Register Immediate Jump
5
MIPS arithmetic

• All instructions have 3 operands
• Operand order is fixed (destination
  first)Example C code A B C MIPS
  code add s0, s1, s2 (associated with
  variables by compiler)

6
MIPS Arithmetic

• C code A B C D E F - A MIPS
  code add t0, s1, s2 add s0, t0,
  s3 sub s4, s5, s0
• Operands must be registers, 32 registers provided
• Design Principle smaller is faster

7
Registers vs. Memory

• Arithmetic instructions operands must be
  registers, 32 registers
• Compiler associates variables with registers

8
MIPS Registers

• Programmable storage
• 232 x bytes of memory
• 31 x 32-bit GPRs (R0 0)
• HI, LO, PC

9
Register Conventions
10
MIPS Operation Overview

• Arithmetic logical
• Add, AddU, Sub, SubU, And, Or, Xor, Nor,
  SLT, SLTU
• AddI, AddiU, SLTi, SLTIU, Andi, Ori, Xori, LUi
• SLL, SRL, SRA, SLLV, SRLV, SRAV
• Memory Access
• LB, LBU, LH, LHU, LW, LWL,LWR
• SB, SH, SW, SWL, SWR

11
MIPS Addressing Modes
12
Typical Operations
13
Operation Summary
Simple instructions dominate load, store add,
subtract move register-register and shift
compare equal, compare not equal branch,
jump call,return
14
Multiply / Divide

• Start multiply, divide
• MULT rs, rt
• MULTU rs, rt (unsigned)
• DIV rs, rt
• DIVU rs, rt (unsigned)
• Move result - multiply, divide
• MFHI rd
• MFLO rd
• Move to HI or LO
• MTHI rd
• MTLO rd

15
Data Types
Bit 0, 1 Bit String sequence of bits of a
particular length 4 bits is a nibble
8 bits is a byte 16 bits is a half-word
32 bits is a word 64 bits is a
double-word Character ASCII 7 bit
code Binary Coded Decimal digits 0-9
encoded as 00002 thru 10012 two decimal
digits packed per 8 bit byte Integers 2's
Complement Floating Point Single
Precision Double Precision
16
Floating Point

• Separate FP Processor
• Separate registers
• add.s add single precision
• add.d add double precision

17
Translation Hierarchy
18
Compiler Process
Figure A.6
19
Assembly Process
Figure A.1
20
Example C Program

• include ltstdio.hgt
• int
• main (int argc, char argv )
• for (i 0 i lt 100 i 1 1) sum sum i
  i
• printf (The sum from 0 .. 100 is d\n , sum)

Program calculates and prints the sum of the
squares of integers from 0 to 100
Figure A.5
21
Machine Language Code
object file
Figure A.2
22
Assembly Language
Note No labels, memory locations, or comments
Figure A.3
23
Figure A.2
24
Assembly Language with Labels
Note the commands that begin with a period are
assembler directives
Figure A.4
25
MIPS Assembly Language
26
Assembly vs. Machine Language

• Assembly provides convenient symbolic
  representation
• much easier than writing down numbers
• e.g., destination first
• Machine language is the underlying reality
• e.g., destination is no longer first
• Assembly can provide 'pseudoinstructions'
• e.g., move t0, t1 exists only in Assembly
• would be implemented using add t0,t1,zero
• When considering performance you should count
  real instructions

27
SPIM

• Simulator for MIPS
• MIPS spelled backwards
• Can read and immediately execute assembly
  language programs
• Self contained
• Contains debugger and few operating system-like
  services

28
SPIM X-Window
Figure A.16
29
MIPS Assembler Syntax

• Numbers are default base 10
• 0x numbers are Hex
• i.e. 0x100 256
• Pseudoinstructions
• Assembler Directives

30
Data Layout Directives - Strings
31
ASCII Standard Code
1100100 - d
32
Addressing Modes
33
MIPS Arithmetic Instructions

• Instruction Example Meaning Comments
• add add 1,2,3 1 2 3 3 operands
• subtract sub 1,2,3 1 2 3 3 operands
• add immediate addi 1,2,100 1 2 100
  constant
• add unsigned addu 1,2,3 1 2 3 3
  operands
• subtract unsigned subu 1,2,3 1 2 3 3
  operands
• add imm. unsign. addiu 1,2,100 1 2 100
  constant
• multiply mult 2,3 Hi, Lo 2 x 3 64-bit
  signed product
• multiply unsigned multu2,3 Hi, Lo 2 x
  3 64-bit unsigned product
• divide div 2,3 Lo 2 3, Lo quotient, Hi
  rem
• Hi 2 mod 3
• divide unsigned divu 2,3 Lo 2
  3, Unsigned quotient rem
• Hi 2 mod 3
• Move from Hi mfhi 1 1 Hi Used to get copy of
  Hi
• Move from Lo mflo 1 1 Lo Used to get copy of
  Lo

34
MIPS Logical Instructions

• Instruction Example Meaning Comment
• and and 1,2,3 1 2 3 3 reg. operands
  Log AND
• or or 1,2,3 1 2 3 3 reg. operands Log
  OR
• xor xor 1,2,3 1 2 Å 3 3 reg. operands
  Log XOR
• nor nor 1,2,3 1 (2 3) 3 reg. operands
  Log NOR
• and immediate andi 1,2,10 1 2 10 Logical
  AND reg, constant
• or immediate ori 1,2,10 1 2 10 Logical OR
  reg, constant
• xor immediate xori 1, 2,10 1 2
  10 Logical XOR reg, constant
• shift left logical sll 1,2,10 1 2 ltlt
  10 Shift left by constant
• shift right logical srl 1,2,10 1 2 gtgt
  10 Shift right by constant
• shift right arithm. sra 1,2,10 1 2 gtgt
  10 Shift right (sign extend)
• shift left logical sllv 1,2,3 1 2 ltlt 3
  Shift left by variable
• shift right logical srlv 1,2, 3 1 2 gtgt 3
  Shift right by variable
• shift right arithm. srav 1,2, 3 1 2 gtgt 3
  Shift right arith. by variable

35
MIPS Data Transfer Instructions

• Instruction Comment
• SW 500(R4), R3 Store word
• SH 502(R2), R3 Store half
• SB 41(R3), R2 Store byte
• LW R1, 30(R2) Load word
• LH R1, 40(R3) Load halfword
• LHU R1, 40(R3) Load halfword unsigned
• LB R1, 40(R3) Load byte
• LBU R1, 40(R3) Load byte unsigned
• LUI R1, 40 Load Upper Immediate
• (16 bits shifted left by 16)

36
Testing Conditions

• Condition Codes
• Processor status bits are set as a side-effect
  of arithmetic instructions (possibly on Moves) or
  explicitly by compare or test instructions.
• ex add r1, r2, r3
• bz label
• Condition Register
• Ex cmp r1, r2, r3
• bgt r1, label
• Compare and Branch
• Ex bgt r1, r2, label

37
MIPS Compare and Branch

• Compare and Branch
• BEQ rs, rt, offset if Rrs Rrt then
  PC-relative branch
• BNE rs, rt, offset ltgt
• Compare to zero and Branch
• BLEZ rs, offset if Rrs lt 0 then PC-relative
  branch
• BGTZ rs, offset gt
• BLT lt
• BGEZ gt
• BLTZAL rs, offset if Rrs lt 0 then branch
  and link (into R 31)
• BGEZAL gt
• Remaining set of compare and branch take two
  instructions
• Almost all comparisons are against zero!

38
MIPS Jmp, Branch, Compare Instructions

• Instruction Example Meaning
• branch on equal beq 1,2,100 if (1 2) go to
  PC4100 Equal test PC relative branch
• branch on not eq. bne 1,2,100 if (1! 2) go
  to PC4100 Not equal test PC relative
• set on less than slt 1,2,3 if (2 lt 3) 11
  else 10 Compare less than 2s comp.
• set less than imm. slti 1,2,100 if (2 lt 100)
  11 else 10 Compare lt constant 2s comp.
• set less than uns. sltu 1,2,3 if (2 lt 3)
  11 else 10 Compare less than natural
  numbers
• set l. t. imm. uns. sltiu 1,2,100 if (2 lt 100)
  11 else 10 Compare lt constant natural
  numbers
• jump j 10000 go to 10000 Jump to target address
• jump register jr 31 go to 31 For switch,
  procedure return
• jump and link jal 10000 31 PC 4 go to
  10000 For procedure call

39
Addresses - Branches - Jumps

• Instructions
• bne t4,t5,Label Next instruction is at Label
  if t4 ? t5
• beq t4,t5,Label Next instruction is at Label
  if t4 t5
• j Label Next instruction is at Label

40
Example Program
Program adds the first 100 positive
integers and displays the result.
Variables s1 - iterations counter
s4 - accumulator for sum a0 - number
of system service add s4, 0, 0
s4 lt- 0, initialize accumulator add s1, 0,
0 s1 lt- 0, initialize iterations
counter Next two instructions mean "While
s1 lt 100 Do" loop slti s2, s1, 101
s1 lt 100 gt s2 lt- 1 beq s2, 0,
end_loop s2 0 gt go to end_loop add s4,
s4, s1 s4 lt- s4 s1, add
number add s1, s1, 1 s1 lt- s1
1, update counter of iterations j loop
go to loop end_loop
add a0, 0, s4 a0 lt- s4, load
result of sum addi v0, 0, 1 v0 lt-
service 1 (data is already in a0) syscall
call to system service
41
(No Transcript)
42
Subroutine Calls Returns
Some machines provide a memory stack as part of
the architecture (e.g., VAX) Sometimes stacks
are implemented via software convention (e.g.,
MIPS)
43
MIPS Instruction Set

• Register zero always has the value zero (even if
  you try to write it)
• Branch/jump and link put the return addr. PC4
  into the link register (R31)
• All instructions change all 32 bits of the
  destination register (including lui, lb, lh) and
  all read all 32 bits of sources (add, sub, and,
  or, )
• Immediate arithmetic and logical instructions are
  extended as follows
• logical immediates ops are zero extended to 32
  bits
• arithmetic immediates ops are sign extended to 32
  bits (including addu)
• The data loaded by the instructions lb and lh are
  extended as follows
• lbu, lhu are zero extended
• lb, lh are sign extended
• Overflow can occur in these arithmetic and
  logical instructions
• add, sub, addi
• it cannot occur in addu, subu, addiu, and, or,
  xor, nor, shifts, mult, multu, div, divu

44
Summary

• 32-bit fixed format inst (3 formats)
• 32 32-bit GPR (R0 contains zero) and 32 FP
  registers (and HI LO)
• partitioned by software convention
• 3-address, reg-reg arithmetic instr.
• Single address mode for load/store
  basedisplacement
• no indirection, scaled
• 16-bit immediate plus LUI
• Simple branch conditions
• compare against zero or two registers

45
Linker
Figure A.8
46
6800 Subroutine Example
LABEL OPCODE OPERAND COMMENT EXAMPLE NAM progr
am name SIZE EQU 04 array size
parameter ORG C100 MAIN PSHB save
state LDAA SIZE array size PSHA push size
parameter LDX R array addr PSHX push addr
parameter JSR ASUM jump to arraysum PULX clear
stack address PULB clear stack
size PULB restore state ABA calculate
Z STAA Z store result ASUM TSX X
SP - 1 LDAB 5,X BMX5 size LDX 3,X XMX
3MX4 CLRA LOOP ADDA ,X AAMX INX n
ext array element DECB loop counter BGT LOOP
RTS Z FCB 0 initialize answer R FCB 1,2,3,
4 initialize array END
subexam.s
47
0001 EXAMPLE NAM program name 0002
0004 SIZE EQU 04 array size
parameter 0003 c100
ORG C100 0004 0005
c100 37 MAIN PSHB save state 0006 c101
86 04 LDAA SIZE array size 0007
c103 36 PSHA push size
parameter 0008 c104 ce c1 20
LDX R array addr 0009 c107 3c
PSHX push addr parameter 0010 c108 bd c1 12
JSR ASUM jump to arraysum 0011 c10b 38
PULX clear stack address 0012
c10c 33 PULB clear stack
size 0013 c10d 33 PULB restore
state 0014 c10e 1b
ABA calculate Z 0015 c10f b7 c1 1f
STAA Z store result 0016
0017 0018
c112 30 ASUM TSX X SP - 1 0019 c113 e6
05 LDAB 5,X BMX5 size 0020
c115 ee 03 LDX 3,X XMX3MX4
0021 c117 4f CLRA 0022 c118 ab
00 LOOP ADDA ,X AAMX 0023 c11a 08
INX next array element 0024 c11b 5a
DECB loop counter 0025 c11c 2e fa
BGT LOOP 0026 c11e 39
RTS 0027 0028
c11f 00 Z FCB 0 initialize
answer 0029 c120 01 02 03 04 R FCB 1,2,3,4 i
nitialize array 0030 END
subexam.lst
48
0001 EXAMPLE NAM program name 0002
0004 SIZE EQU 04 array size
parameter 0003 c100
ORG C100 0004 0005
c100 37 MAIN PSHB save state 0006 c101
86 04 LDAA SIZE array size 0007
c103 36 PSHA push size
parameter 0008 c104 ce c1 20
LDX R array addr 0009 c107 3c
PSHX push addr parameter 0010 c108 bd c1 12
JSR ASUM jump to arraysum 0011 c10b 38
PULX clear stack address 0012
c10c 33 PULB clear stack
size 0013 c10d 33 PULB restore
state 0014 c10e 1b
ABA calculate Z 0015 c10f b7 c1 1f
STAA Z store result 0016
0017 0018
c112 30 ASUM TSX X SP - 1 0019 c113 e6
05 LDAB 5,X BMX5 size 0020
c115 ee 03 LDX 3,X XMX3MX4
0021 c117 4f CLRA 0022 c118 ab
00 LOOP ADDA ,X AAMX 0023 c11a 08
INX next array element 0024 c11b 5a
DECB loop counter 0025 c11c 2e fa
BGT LOOP 0026 c11e 39
RTS 0027 0028
c11f 00 Z FCB 0 initialize
answer 0029 c120 01 02 03 04 R FCB 1,2,3,4 i
nitialize array 0030 END
subexam.lst
49
MIPS Reads - Writes
Figure A.4
50
Different Instruction Sets

• Accumulator
• operands are in memory and are used in
  conjunction with what is on the accumulator - eg.
  6800
• Load-store
• operands are loaded onto registers from memory
  then manipulated - eg. MIPS

Problems 3.19 3.20
51
Problem Assumptions

• Opcode is 1 byte
• memory addresses are 2 bytes
• Data is 4 bytes
• Instructions are an integral of bytes
• No optimizations to reduce memory traffic

Problems 3.19 3.20
52
Calculate a b c
Problems 3.19 3.20
53
Machine Categories
54
End of Set 6