Verilog II CPSC 321

1
Verilog IICPSC 321

• Andreas Klappenecker

2
Todays Menu

• Verilog,
• Verilog,
• Verilog

3
Modules

• module mod_name (parameters)
• input
• output
• reg
• endmodule

4
Full Adder

• module fulladd(cin, x, y, s, cout)
• input cin, x, y
• output s, cout
• assign s x y cin
• assign cout (x y) (cin x) (cin y)
• endmodule

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Full Adder

• module fulladd(cin, x,y,s, cout)
• input cin, x, y
• output s, cout
• assign cout, s x y cin
• endmodule
• The assign statement assigns the MSB to cout
• and the LSB to s.

6
Hello World

• module top
• initial
• display("Hello, world!")
• endmodule
• initial statements are executed once by the
  simulator

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Vector wires

• Range msb lsb
• wire 30 S
• S 4b0011
• The result of this assignment is
• S3 0, S2 0, S1 1, S0 1
• wire 12 A
• A S21
• means A1 S2, A2 S1

8
Variables

• Variables come in two flavors
• reg
• integers
• reg can model combinatorial or sequential parts
  of the circuits
• reg does not necessarily denote a register!
• Integers often used as loop control variables
• useful for describing the behavior of a module

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Simple Example

• module testgate
• reg b, c // variables
• wire a, d, e // nets
• and (d, b, c) // gates
• or (e, d, c) //
• nand(a, e, b) //
• initial begin // simulated once
• b1 c0 // blocking assignments
• 10 display("a b", a)
• end
• endmodule What value will be printed?

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Operators

• 1s complement A
• 2s complement -A
• bitwise AND AB
• reduction A produces AND of all bits in A
• Concatenate a,b,c
• a,b,c a b c
• Replication operators 2A A,A
• 2A,3B A,A,B,B,B

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Continuous assignments

• Single bit assignments
• assign s x y cin
• assign cout (x y) (cin x) (cin y )
• Multibit assignments
• wire 13 a,b,c
• assign c a b

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Always Blocks

• An always block contains one or more procedural
  statements
• always _at_(sensitivity list)
• always _at_(x or y)
• begin
• s x y
• c x y
• end

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Mux Structural Verilog
module mux(f, a,b,sel) input a,b,sel
output f wire f1, f2 not(nsel, sel)
and(f1, a,nsel) and(f2, b, sel) or (f, f1,
f2) endmodule
b
f
a
sel
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Mux Dataflow Model

• module mux2(f, a,b,sel)
• output f
• input a,b,sel
• assign f (a sel) (b sel)
• endmodule

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Mux Behavioral Model

• module mux2(f, a,b,sel)
• output f
• input a,b,sel
• reg f
• always _at_(a or b or sel)
• if (sel1)
• f b
• else
• f a
• endmodule

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Sign extension and addition

• module adder_sign(x,y,s,ss)
• input 30 x,y
• output 70 s, ss
• assign s x y,
• ss 4x3,x4y3,y
• endmodule
• x 0011, y 1101
• s 0011 1101 00010000
• ss 0011 1101 00000011 11111101 00000000

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Demux Example

• 2-to-4 demultiplexer with active low

enable a b z3 z2 z1 z0
0 x x 1 1 1 1
1 0 0 1 1 1 0
1 1 0 1 1 0 1
1 0 1 1 0 1 1
1 1 1 0 1 1 1
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Demux Structural Model
enable a b z3 z2 z1 z0
0 x x 1 1 1 1
1 0 0 1 1 1 0
1 1 0 1 1 0 1
1 0 1 1 0 1 1
1 1 1 0 1 1 1

• // 2-to-4 demultiplexer
• module demux1(z,a,b,enable)
• input a,b,enable
• output 30 z
• wire abar,bbar
• not v0(abar,a), v1(bbar,b)
• nand (z0,enable,abar,bbar)
• nand (z1,enable,a,bbar)
• nand (z2,enable,abar,b)
• nand (z3,enable,a,b)
• endmodule

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Demux Dataflow model
enable a b z3 z2 z1 z0
0 x x 1 1 1 1
1 0 0 1 1 1 0
1 1 0 1 1 0 1
1 0 1 1 0 1 1
1 1 1 0 1 1 1

• // 2-to-4 demux
• // dataflow model module
• demux2(z,a,b,enable)
• input a,b,enable
• output 30 z
• assign z0 enable,a,b
• assign z1 (enable a b)
• assign z2 (enable a b)
• assign z3 enable ? (a b) 1'b1
• endmodule

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Demux Behavioral Model

• // 2-to-4 demultiplexer with active-low outputs
• module demux3(z,a,b,enable)
• input a,b,enable
• output 30 z
• reg z // not really a register!
• always _at_(a or b or enable)
• case (enable,a,b)
• default z 4'b1111
• 3'b100 z 4'b1110
• 3'b110 z 4'b1101
• 3'b101 z 4'b1011
• 3'b111 z 4'b0111
• endcase
• endmodule

enable a b z3 z2 z1 z0
0 x x 1 1 1 1
1 0 0 1 1 1 0
1 1 0 1 1 0 1
1 0 1 1 0 1 1
1 1 1 0 1 1 1
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Always Blocks

• The sensitivity list _at_( ) contains the events
  triggering an evaluation of the block
• _at_(a or b or c)
• _at_(posedge a)
• _at_(negedge b)
• A Verilog compiler evaluates the statements in
  the always block in the order in which they are
  written

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Assignments

• If a variable is assigned a value in a blocking
  assignment
• a b c
• then subsequent references to a contain the new
  value of a
• Non-blocking assignments lt
• assigns the value that the variables had while
  entering the always block

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D Flip-flop

• module D_FF(Q,D,clock)
• output Q
• input D, clock
• reg Q
• always _at_(negedge clock)
• Q lt D
• endmodule

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Clock

• A sequential circuit will need a clock
• supplied by the testbed
• Clock code fragment
• reg clock
• parameter period 100
• initial clock 0
• always _at_(period/2)
• clock clock

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D-Flipflop with Synchronous Reset

• module flipflop(D, Clock, Resetn, Q)
• input D, Clock, Resetn
• output Q
• reg Q
• always _at_(posedge Clock)
• if (!Resetn)
• Q lt 0
• else
• Q lt D
• endmodule // 7.46 in BV

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Gated D-Latch

• module latch(D, clk, Q)
• input D, clk
• output Q
• reg Q
• always _at_(D or clk)
• if (clk)
• Q lt D
• endmodule
• Missing else clause gt a latch will be
  synthesized to keep value of Q when clk0

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Shift Register What is wrong here?

• module example(D,Clock, Q1, Q2)
• input D, Clock
• output Q1, Q2
• reg Q1, Q2
• always _at_(posedge Clock)
• begin
• end
• endmodule

Q1 D Q2 Q1
Q1 D Q2 Q1 // DQ1Q2
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Shift register Correct Version

• module example(D,Clock, Q1, Q2)
• input D, Clock
• output Q1, Q2
• reg Q1, Q2
• always _at_(posedge Clock)
• begin
• Q1 lt D
• Q2 lt Q1
• end
• endmodule

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Rule of Thumb

• Blocking assignments are used to describe
  combinatorial circuits
• Non-blocking assignments are used in sequential
  circuits

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n-bit Ripple Carry Adder

• module ripple(cin, X, Y,
• S, cout)
• parameter n 4
• input cin
• input n-10 X, Y
• output n-10 S
• output cout
• reg n-10 S
• reg n0 C
• reg cout
• integer k

always _at_(X or Y or cin) begin C0 cin
for(k 0 k lt n-1 kk1) begin
Sk XkYkCk Ck1 (Xk
Yk) (CkXk)(CkYk) end
cout Cn end endmodule
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Loops and Integers

• The for loop is used to instantiate hardware
  modules
• The integer k simply keeps track of instantiated
  hardware
• Do not confuse integers with reg variables

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Bit-Counter

• Count the number of bits having value 1 in
  register X
• Again an example for parameters
• Another example of a for loop

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Bit Counter

• module bit_cnt(X,Count)
• parameter n 4
• parameter logn 2
• input n-10 X
• output logn0 Count
• reg logn0 Count
• integer k

always _at_(X) begin Count 0
for(k0kltnk k1) CountCountXk
end endmodule
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Blocks of Procedural Code

• initial
• executed once at the beginning of simulation
• initial display(Hello World)
• always
• repeatedly executed
• begin-end
• sequential execution of block statements
• delays add up
• fork-join blocks
• concurrent execution of statements

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Concurrency Example
Block 2 stmt 1 Block 1 stmt 1 Block 1 stmt
2 Block 2 stmt 2 Block 1 stmt 3 Block 2 stmt 3

• module concurrency_example
• initial begin
• 1 display(Block 1 stmt 1")
• display(Block 1 stmt 2")
• 2 display(Block 1 stmt 3")
• end
• initial begin
• display("Block 2 stmt 1")
• 2 display("Block 2 stmt 2")
• 2 display("Block 2 stmt 3")
• end
• endmodule

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Concurrency Example
Block 2 stmt 1 Block 1 stmt 1 Block 1 stmt
2 Block 2 stmt 2 Block 1 stmt 3 Block 2 stmt 3

• module concurrency_example
• initial begin
• 1 display(Block 1 stmt 1")
• display(Block 1 stmt 2")
• 2 display(Block 1 stmt 3")
• end
• initial begin
• display("Block 2 stmt 1")
• 2 display("Block 2 stmt 2")
• 2 display("Block 2 stmt 3")
• end
• endmodule

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Concurrency fork and join
Block 1 stmt 2 Block 2 stmt 1 Block 1 stmt
1 Block 1 stmt 3 Block 2 stmt 2 Block 2 stmt 3

• module concurrency_example
• initial fork
• 1 display(Block 1 stmt 1")
• display(Block 1 stmt 2")
• 2 display(Block 1 stmt 3")
• join
• initial fork
• display("Block 2 stmt 1")
• 2 display("Block 2 stmt 2")
• 2 display("Block 2 stmt 3")
• join
• endmodule

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Displaying Results

• a 4b0011
• display(The value of a is b, a)
• The value of a is 0011
• display(The value of a is 0b, a)
• The value of a is 11
• If you you display to print a value that is
  changing
• during this time step, then you might get the new
  or
• the old value use strobe to get the new value

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Displaying Results

• Standard displaying functions
• display, write, strobe, monitor
• Writing to a file instead of stdout
• fdisplay, fwrite, fstrobe, fmonitor
• Format specifiers
• b, 0b, d, 0d, h, 0h, c, s,

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Display Example
module f1 integer f initial begin f
fopen("myFile") fdisplay(f, "Hello, bla
bla") end endmodule
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Moore Machines
next state logic
present state register
output logic
input

• The output of a Moore machine depends
• only on the current state. Output logic and
• next state logic are sometimes merged.

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Coding Moore Machines

• The logic in the Moore machine can be described
  by two case statements
• (one case statement if logic blocks are
  merged)
• Enumerate all possible states of input and
  current state, and generate the output and next
  state
• Give states meaningful names using define or
  parameters

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Moore Machine Example

• Automatic food cooker
• Has a supply of food
• Can load food into the heater when requested
• Cooker unloads the food when cooking done

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Automated Cooker

• Outputs from the machine
• load signal that sends food into the cooker
• heat signal that turns on the heater
• unload signal that removes food from cooker
• beep signal that alerts that food is done

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Automated Cooker

• Inputs
• clock
• start start the load, cook, unload cycle
• temp_ok temperature sensor detecting when
  preheating is done
• done signal from timer when done
• quiet Should cooker beep?

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Cooker

• module cooker(
• clock, start, temp_ok, done, quiet, load, heat,
  unload, beep
• )
• input clock, start, temp_ok, done, quiet
• output load, heat, unload, beep
• reg load, heat, unload, beep
• reg 20 state, next_state

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Defining States

• define IDLE 3'b000
• define PREHEAT 3'b001
• define LOAD 3'b010
• define COOK 3'b011
• define EMPTY 3'b100

You can refer to these states as IDLE,
PREHEAT, etc.
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State Register Block

• define REG_DELAY 1
• always _at_(posedge clock)
• state lt (REG_DELAY) next_state

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Next State Logic

• always _at_(state or start or temp_ok or done)
• // whenever there is a change in input
• begin
• case (state)
• IDLE if (start) next_statePREHEAT
• PREHEAT if (temp_ok) next_state LOAD
• LOAD next_state COOK
• COOK if (done) next_stateEMPTY
• EMPTY next_state IDLE
• default next_state IDLE
• endcase
• end

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Output Logic

• always _at_(state)
• begin
• if(state LOAD) load 1 else load 0
• if(state EMPTY) unload 1 else unload 0
• if(state EMPTY quiet 0) beep 1
• else beep 0
• if(state PREHEAT
• state LOAD
• state COOK) heat 1
• else heat 0
• end