CS535 Final Project: ATAPI aka IDE Interface within an FPX Module

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CS535 Final ProjectATAPI (aka IDE) Interface
within an FPX Module

• December 4, 2001
• Benjamin West
• Computer Communications Research Center (CCRC)
• Qiong (Maggie) Zhang
• Magnetic Information Sciences Center (MISC)
• http//students.cec.wustl.edu/bmw3/hwdb/cs535.sht
  ml

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Project Background

• Our research project aims to modify off-the-shelf
  hard drive to accept simple search queries,
  perform search at or near disk rotation speed.
• Difficult to obtain proprietary information about
  hard drive internals, so we start with drives
  interface to host machine (ATAPI), a published
  standard.
• As intermediate step in project passively snoop
  data bursts on ATAPI bus, performing search on
  snooped data.

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Project Goals

• To directly observe traffic that traverses ATAPI
  bus, capturing contents of data packets sent from
  ATAPI-attached hard drive.
• To encapsulate captured data into ATM cells,
  allowing easy reuse of cell buffering and
  transport schemes from MP5.
• To transmit cells with captured data from FPX to
  observer on a remote console (i.e. over known VC).

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Delegation

• Maggie
• VHDL Coding/Simulation of ATAPI state machine
• of ATM encapsulation of ATAPI data.
• of SDRAM-based FIFO with Get/Push/Pull/Send
  Cell processes
• Ben
• Construction/Verification of Hardware
  Daughterboard,
• Setup Host of PC with ATAPI Controller and Test
  Hard Drive.
• Assist Testing/Simulation of FPX module as a
  whole.

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Overall Block Diagram
Host ATAPI Controller

FPX
RAD
NID
Loopback module
ATAPI bus
ATAPI_to_ATM module
32 RAD test pins
15bit CTRL
Tap
16bit Data
Hard drive
Custom PCB for Electrical Termination 5V to
3.3V Conversion
Setup reused from MP5
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ATAPI_to_ATM module(modified Pacer from MP5)
To SDRAM Controller
ATAPI_to_ATM module
From ATAPI
Data_TESTPINS
ATAPI FSM
Out to NID
Clk_en_word_rad
Cell Fifo
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Control_TESTPINS
Soc_out
ReadRequest
WriteRequest
Data_IDE
16
Tcaff_in
WriteGrant
ReadGrantt
32
Data_in
From NID
Data_out
ReadeData
WriteData
32
Soc_in
64
64
32
Tcaff_out
Get Cell
Push Cell
Pull Cell
Send Cell
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ATAPI FSM
init_IDE0
Signal init_IDE set by sending control cell like
mp5
IDLE
Init_IDE1
MonitorDMA
STOP1
DMARQ1 DMACK1 STOP0 HDMARDY1
UDMA0
DSTROBE edge / Sample data
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GetCell FSM(modified from MP5)
Reset
WriteGrant1 InCellEmpty1
Request
If Soc_in1 then NextStatew1 buffer
data from network Elsif data from IDE FSM
NextStatew1 buffer Data from DATA_IDE
w1
w13
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Custom PCB
2x40pin RAD test connectors
40pin ATAPI connector
Termination resistors
74AC245Buffers/Transceivers
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Status

• VHDL
• The ATAPI_to_ATM module works under simulation,
  using test waveforms drawn from ATAPI spec.
• Next few slides illustrate.

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Control cells coming in
Control cell coming in with opcode 18
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Control cells coming out
ATM FSM Initialized
Control cell going out
State goes to monitorIDE
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Control cells coming out
Clean sampled data with clock
Input from Test pins (IDE bus) (must sample at
the right time to avoid ambiguity)
IDE bus Control signals
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Control cells coming out
Raw ATM Cell Output
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Status (part 2)

• HARDWARE
• The custom PCB does NOT work (yet). Apparently
  introduces severe interference into ATAPI bus,
  preventing proper operation of hard drive and
  controller.
• Electrical termination issue is suspected, and
  thus still a work in progress.

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Results?

• NONE! (yet)
• Havent had our lab time yet...