Dramatic Chip Cost Reduction Using New I/O Circuits

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Dramatic Chip Cost Reduction Using New I/O
Circuits
CMOS ET, Vancouver, 2009
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Background
Wireless I/O Smart Solutions for Dramatic
Productivity Improvements
As devices become more integrated, they can
become dramatically more expensive. the
proportion of the overall device cost attributed
to final test can be as high as 30 percent. Chip
companies need to recoup development costs. Rob
Hilkes, Semiconductor Insights
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Overview

• Increase productivity by 9.7
• Decrease mfg and test costs by 18.6
• Total benefit of 28.3

If people are not investigating the use of
non-contact technologies at 45nm they are in
denial. Marc Mangrum, Mgr. Advanced Packaging
Test Technologies,WMSG, Freescale Semiconductor
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Scanimetrics Solution

• Inductive chip-scale communications
• Micro TX/RX on chip
• One Tx/Rx per I/O
• High speed
• Low power
• Pitch scales to lt20um

Chip A
Chip B
Scanimetrics is proposing a truly unique
application for wafer test. William Mann, Chair,
IEEE Semiconductor Wafer Test Workshop
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Scaling Problems
Active Circuit
Pad Frame
250nm
180nm
130nm
90nm
65nm
45nm

• Probe and I/O pads occupy increasingly higher
  percentage of area
• White space is often filled with non-value added
  circuitry

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Manufacturing and I/O Problems

• Bond / probe pads are not shrinking with circuit
  dimensions according to Moores Law
• Probes
• Pitches not shrinking, tip sizes not changing
• Pad Damage
• Maximum allowable damaged area is decreasing
• ESD structures affect signal speed and power
  consumption

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Applications

• 3D Packaging - replace TSVs and add testability
  to 3D structure
• Non-contact testing of wafers

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Productivity Increases with Scanimetrics
Wireless I/O
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Yield Improvement

• Application Device
• Device has 250 power/gnd pins
• Device has 600 test/signals pins
• 10 of these pins are test-only-pins, not bonded
  out for final packaging
• Device size 8 mm x 8 mm
• Yield loss due to pad damage by probe needles is
  6

Yield loss up to 20, Improved Flip Chip
Probing, by Terence Collier, CvInc.
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Yield Improvement

• Yield Improvement related to pad damage
• Replace 600 signal/test pins with contactless
  WiTAP
• Yield loss due to pad damage for 250 contact
  pins 6 x (250/850) 1.8
• Yield improvement 4.2

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Yield Improvement

• Yield Improvement related to reduced area
• Test-only-pins are accessed via WiTAP wirelessly
• Test-only-pins can be placed anywhere inside the
  chip
• No need to connect these pins to standard I/O
  cells at the perimeter of the chip
• Test nodes are accessible during wafer probing as
  well as after packaging
• Yield improvement due to area reduction 3.1

Based on Poisson Yield Model
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Chip Area Reduction

• Yield Improvement related to reduced area
• Test-only pins replaced by WiTAP and relocated
  inside the chip
• of total area and cost reduction 13.2

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Chip Area Reduction
Antenna Area (36 µm x 50 µm)
WiTAP Transceiver circuitry (12 µm x 36 µm)
Connection from Transceiver to Antennas
Test-only-pin with wireless probe pad
Hybrid I/O cell with bond and wireless probe pad
Standard I/O cell with bond and probe pad
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Shorter time-to-market

• First-silicon validation is the least predictable
  and the most time-consuming part (gt 35) of the
  development cycle of a new chip
• Study shows when a product is shipped six
  months late, profit is adversely impacted by 33
  on average

• WiTAP allows internal debug signals (such as
  FIFO_FULL WRITE) to be made observable and
  capturable in post-silicon validation
• WiTAP reduces post-silicon validation time up to
  20

A New Approach to In-System Silicon Validation
and Debug, M. Abramovici, P. Bradley Tackling
limited-access test problems with boundary-scan,
www.jtag.com Based on AMD design engineering
source
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Test Cost Reduction
Based on ISMI Cost of Test Model
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Test Cost Reduction

• Test cost is 5 to 10 of production cost
• Compared to cantilever probe cards, WiTAP is 54
  more cost effective
• Therefore, overall production cost savings of
  2.7 to 5.4 can be realized using WiTAP

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Faster Yield Ramp-up

• Extra test points allow functional tests during
  wafer test, in addition to structural tests by
  boundary-scan
• Higher test coverage and source of failure are
  identified earlier
• Reduced number of false-good chips that go into
  packaging
• For a product with 18 month life and 6 month
  yield ramp, reducing yield ramp by 2 months
  results in 1.4 additional revenue

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Summary of Productivity Improvement
Productivity Increase Comparable to a Die Shrink
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Thank You
Contact the Scanimetrics team with any questions

Chris Sellathamby, Ph.D., PEngVP Sales
Marketingcsellathamby_at_scanimetrics.com Phone
780 433 9441Toll Free 866 747 9441Fax 780 433
9499