FIR filters - PowerPoint PPT Presentation

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FIR filters

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Design an N-tap transposed linear-phase FIR filter as a sequential application ... Use only one multiplier and show how processing time can be decreased twice. ... – PowerPoint PPT presentation

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Title: FIR filters


1
FIR filters
  • ELG6163
  • Miodrag Bolic

2
Outline
  • FIR filters
  • Structures
  • Polyphase FIR filters
  • Parallel polyphase FIR
  • Decimated FIR
  • Implementations of FIR filters

3
Sequential application specific processor
  • A processor tuned only for a particular
    application
  • Can be used for low-power implementations
  • Word lengths can be adjusted to the current
    problem.
  • Example FIR filter

4
Direct form FIR filter
Copied from Wanhammer99
5
Transposed FIR
Copied from Wanhammer99
6
Assignment
  • Design an N-tap transposed linear-phase FIR
    filter as a sequential application specific
    processor. Use only one multiplier and show how
    processing time can be decreased twice.
  • Hint design a transposed FIR filter structure
    as in the previous slide but allow for generating
    the sums in reversed order PSN-1, PSN-2, , PS1,
    y(n).

Copied from Wanhammer99
7
General purpose processor architecture
  • FIR example
  • We will study RISC architectures
  • Single-cycle processor
  • Implementation of add and load instructions
  • Pipelined implementation
  • Why do all instructions have the same number of
    cycles

8
Example Digital Filtering
  • The basic FIR Filter equation is
  • Where hk is an array of constants

yn0 For (n0 nltNn) For (k
0kltNk) //inner loop yn yn
hkxn-k
Only Multiply and Accumulate (MAC) is needed!
In C language
Copied from Rony Ferzli http//www.fulton.asu.edu
/karam/eee498/
9
MAC using General Purpose Processor (GPP)
11
12
3
R0
11
24
9
R2
44
X
R1
1
2
3
Clr A Clear Accumulator A
Clr B Clear Accumulator B
Loop Mov R0, Y0 Move data from memory location 1 to register Y0
Mov R1,X0 Move data from memory location 2 to register X0
Mpy X0,Y0,A X0Y0 -gtA
Add A,B A B -gt B
Inc R0 R0 1 -gt R0
Inc R1 R1 1 -gt R1
Dec N Dec N (initially equals to 3)
Tst N Test for the value
Jnz Loop Different than zero loop again
Mov B,R2 Move result to memory
Copied from Rony Ferzli http//www.fulton.asu.edu
/karam/eee498/
10
MAC using DSP
  • Harvard Architecture allows multiple memory reads

11
12
3
11
24
9
R2
44
X
1
2
3
Clr A Clear Accumulator A
Rep N Rep N times the next instruction
MAC (R0), (R1), A Fetch the two memory locations pointed by R0 and R1, multiply them together and add the result to A, the final result is stored back in A
Mov A, R2 Move result to memory
Copied from Rony Ferzli http//www.fulton.asu.edu
/karam/eee498/
11
Copied from DSPPrimer-Slides
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