20 Debounce

1
Debouncing a Switch

• A Design Example

2
Background and Motivation
3
When you throw a switch (button or two-pole
switch)

• It often bounces

4
Another switch
switch
afterinversion
5
Yet Another
6
Still Yet Another
7
Causes

• Switches and buttons are mechanical
• Spring loaded
• Contacts literally bounce
• Not an instant, once-only, on?off change

8
Source of Errors

• Consider a 100 MHz system clock, which has a 10
  ns period
• Each ms would be 100,000 system clock cycles
• Downstream circuitry will see every bounce as an
  input change!

1 ms 100,000 clock cycles at 100 MHz
9
FSM-Based Solution
10
Solutions

• Single-output switch
• Since all you see is bouncing value, timing-based
  solution can be employed
• There are other solutions but they require a
  different kind of switch

11
Timing-Based Solution

• Only declare an input change after signal has
  been stable for at least 5ms

5ms
12
FSM Solution

• Simple enough that an FSM might not be required
• Easy to concoct a sequential circuit to do this
  with a counter and a single FF
• Lets do it with an FSM
• If solution requires only a counter and a single
  FF, we will find that solution

13
Draw a Simplified Timing Diagram
14
Draw a System Block Diagram
noisy
debounced
FiniteStateMachine
Timer (5ms)
clrTimer
timerDone
clk
clk
reset
Very reminiscent of our car wash controller
15
The Design of the FSM
16
Draw a State Graph
noisy
clrTimer
S0
noisy
noisytimerDone
noisy
S3
S1
noisytimerDone
noisytimerDone
debounced
noisy
noisytimerDone
noisy
S2
debounced clrTimer
noisy
17
Draw a State Graph
noisy
Debounced outputis low
clrTimer
S0
noisy
noisytimerDone
noisy
S3
S1
noisytimerDone
noisytimerDone
debounced
noisy
noisytimerDone
noisy
S2
debounced clrTimer
noisy
18
Draw a State Graph
noisy
Debounced outputis high
clrTimer
S0
noisy
noisytimerDone
noisy
S3
S1
noisytimerDone
noisytimerDone
debounced
noisy
noisytimerDone
noisy
S2
debounced clrTimer
noisy
19
An Improved State Graph
Looks like the FSMcan be implementedwith just a
single FF
noisy/clrTimer
Do you see why there is noneed for a reset input?
S0
noisytimerDone
noisytimerDone
noisytimerDone
S1
debounced
noisytimerDone
As mentioned, Mealymachines often requirefewer
states
noisy/clrTimer
20
Reduce FSM to Logic

• S0 CS S1 CS noisy N timerDone
  T

N T
CS
00
01
11
10
0
1
1
1
1
1
NS noisytimerDone CStimerDone clrTimer
noisyCS noisyCS debounced CS
21
Reduce FSM to Logic
NS noisytimerDone CStimerDone clrTimer
noisyCS noisyCS debounced CS
noisy
debounced
timerDone
CS
clrTimer
noisy
22
Input noisy is Asynchronous
If pulse shorter than period, FSM may not see it

• Very small pulses may be missed by FSM
• This is not a real problem so we will live with it

23
More on Asynchronous noisy Input
noisy
debounced
FiniteStateMachine
Timer (5ms)
clrTimer
timerDone
clk
clk
reset

• This is the classic asynchronous input problem
• FSM may see input change and change state
• Timer may not see input change and not clear
  timer
• Or vice versa
• Will this cause incorrect operation?

24
Asynchronous Input Problem
noisy/clrTimer
noisytimerDone
S0
Look at the transitions. Will previous slides
problem cause a malfunction? If you determine
that a problem may result, that is easiest way to
solve the problem?
noisytimerDone
noisytimerDone
S1
debounced
noisytimerDone
noisy/clrTimer
25
More on Asynchronous noisy Input

• What about metastability?
• Most buttons arent pushed very often
• Chance of metastability is very low
• We could eliminate all our asynchronous problems
  by adding flip flops in series
• Avoid detailed analysis
• Play it safe and avoid possibility of mistakes

26
Design of the Timer
27
Timer Calculations

• Assume system runs at 50 MHz (20 ns period)
• 5ms/20ns 250,000 system clock cycles
• We could design a MOD-250,000 counter
• A simple 18-bit counter will work
• 218 is a bit longer than 250,000 (262,144)
• It is close enough to 5 ms for our purposes

28
Design the Timer

• 19 input state machine
• 18 CS bits 1 clrTimer bit
• Very, very large truth table
• A better approach
• Register that selects between CS1 and 0
• This is the technique of Chapter 12 (registers)

29
Timer Structure
18
1
18
timerDone
18
18
18-inputAND
18
0
clrTimer
clk
What can we do to simplify this circuit?
30
Timer Structure
18
1
18
timerDone
18
18
18-inputAND
18
0
clrTimer
clk
What can we do to simplify this circuit?
31
Improved Timer Structure
18
1
18
timerDone
18
18
18-inputAND
18
clrTimer
clk
This is a simpler way to conditionally generate
zeroes.
A synthesis tool likely would have generated
this from Verilog orVHDL code containing a MUX
32
Timer Structure
18
1
18
timerDone
18
18
18-inputAND
18
0
clrTimer
clk
What can we do to simplify this circuit?
33
Improved Timer Structure
18
1
18
18
18
clrTimer
Cout
clk
timerDone
Use the carry out of the adder to detect
rollover. Output timerDone is delayed by one
cycle, but this is not a problem in our system.
34
Building the 1 Circuit Version 1
count170
000000000000000001
output
The adder could be built as outlined back in
Chapter 8 using full adder blocks. However, half
the full adder inputs will be 0. There ought to
be a better way! Hint Any time a circuit has
constant inputs (0 or 1) then the circuit can be
simplified!
35
A Full-Adder with 0 Inputs
Full Adder
Half Adder
A
A
S
0
S
Cin
Cin
0
A
0
A
0
Cout
0
Cout
Cin
Cin
A
Cin
Half Adder adds two bits instead of three
36
Building the 1 Circuit - Version 2
A0
A1
A2
HalfAdder
HalfAdder
HalfAdder
C0
C1
C2
1
Carry-in of 1 gives us the 1
S0
S1
S2
37
Building an 18-Bit AND
This is one way
CAD tools are good at building structures like
this from lower-level building blocks. Just
describe the AND in Verilog or VHDL and CAD tools
will make a good choice. If target technology
has special structures for wide logic, CAD tools
likely will use it
38
Debouncer Summary

• Structure is timer FSM
• 2-state FSM makes NS logic trivial
• Asynchronous input noisy means we must be sure
  our system works with any input timing
• If desired/needed, synchronize noisy input
  using one or more flip flops
• Counter too large for conventional techniques
• Use MUX register technique of Chapter 12
• Systems can usually be greatly simplified beyond
  the obvious design by using careful analysis