chapter six transparency

1
Chapter 7 Parallel I/O Ports
The 68HC11 Microcontroller
Han-Way Huang
Minnesota State University, Mankato
2
Basic I/O Concepts
Peripheral devices Pieces of equipment that
exchange data with a computer. Examples include
switches, light-emitting diodes, cathode-ray
tube screens, printers, modems, keyboards, and
disk drives. Interface (peripheral) chip - A
chip whose function is to synchronize data
transfer between the CPU and I/O devices. - An
interface may consist of control registers,
status registers, data direction latches, and
control circuitry. - An interface chip has pins
that are connected to the CPU and I/O port pins
that are connected to the I/O devices. - Each
interface chip has a chip enable signal input or
inputs, when asserted, allow the interface chip
to react to the data transfer request. - Data
transfer between an I/O device and the CPU can be
proceeded bit-by-bit or in multiple bits.
3
(No Transcript)
4
I/O Schemes 1. Isolated I/O scheme - The
microprocessor has dedicated instructions for I/O
operations - The microprocessor has a separate
address space for I/O devices 2. Memory-mapped
I/O scheme - The microprocessor uses the same
instruction set for I/O operations - The I/O
devices and memory components are resident in the
same memory space
5
I/O Transfer Synchronization The role of an
interface chip 1. Synchronizing data transfer
between CPU and interface chip. 2. Synchronizing
data transfer between interface chip and I/O
device.
6
Synchronizing the Microprocessor and the
Interface Chip The polling method 1. for input
-- the microprocessor checks a status bit of the
interface chip to find out if the interface
chip has received new data from the input
device. 2. for output -- the microprocessor
checks a status bit of the interface chip to find
out if it can send new data to the interface
chip. The interrupt-driven method 1. for input
-- the interface chip interrupts the
microprocessor whenever it has received new data
from the input device. 2. for output -- the
interface chip interrupts the microprocessor
whenever it can accept new data from the
microprocessor.
7
Synchronizing the Interface Chip and the I/O
Devices Brute-force method -- useful when the
data timing is unimportant 1. for input --
nothing special is done. The microprocessor
reads the interface chip and the interface chip
returns the voltage levels on the input port pins
to the microprocessor. 2. for output -- nothing
special is done. The interface chip places the
data that it received from the microprocessor
directly on the output port pins. The strobe
method -- a strobe signal is used to indicate
that data are stable on I/O port pins 1. for
input -- the interface chip latches the data into
its data register using the strobe signal. 2. for
output -- the interface chip places the data on
port pins that it received from the
microprocessor and asserts the strobe signal.
The output device latches the data using the
strobe signal. The handshake method -- used
when timing is crucial - two handshake signals
are used to synchronize the data transfer. One
signal, call it H1, is asserted by the interface
chip. The other signal, call it H2, is asserted
by the I/O device. - two handshake modes are
available -- pulse mode and interlocked mode.
8
Input Handshake Protocol Step 1. The interface
chip asserts (or pulses) H1 to indicate its
intention to input data. Step 2. The input device
puts data on the data port pins and also asserts
(or pulses) the handshake signal H2. Step 3.
The interface chip latches the data and
de-asserts H1. After some delay, the input
device also de-asserts H2.
9
Output Handshake Protocol Step 1. The interface
chip places data on the port pins and asserts (or
pulses) H1 to indicate that it has valid data to
be output. Step 2. The output device latches the
data and asserts (or pulses) H2 to acknowledge
the receipt of data. Step 3. The interface chip
de-asserts H1 following the assertion of H2. The
output device then de-asserts H2.
10
68HC11 Parallel I/O Overview - The 68HC11A8 has
40 I/O pins that are arranged in five I/O
ports. - All I/O pins serve multiple
functions. - Ports A, B, and E with the exception
of port A pin 7 are fixed-direction inputs or
outputs. - Ports C and D are bi-directional I/O
pins under the control of their associated
data direction registers. - Port C, port B, the
STRA pin, and the STRB pin are used for strobed
and handshake parallel I/O, as well as for
general-purpose I/O. Port Registers - To input,
the 68HC11 reads from the port data register - To
output, the 68HC11 writes into the port data
register - All except port C have one data
register PORTA (at 1000) PORTB (at
1004) PORTC (at 1003) PORTCL (at
1005) PORTD (at 1008) PORTE (at 100A)
11
Fixed Direction I/O (ports A, B, and E) To input
from an input port, execute a load instruction
with the port data register as the source
operand. For example, the following instruction
sequence reads a byte from port
E REGBAS equ 1000 I/O register block base
address PORTE equ 0A offset of port E data
register from REGBAS ldx REGBAS ldaa PORTE,X
To output a byte to an output port, write to the
port data register directly. For example, the
following instruction sequence outputs the value
38 to port B REGBAS equ 1000 I/O register
block base address PORTB equ 04 offset of port
B data register from REGBAS ldx REGBAS ldaa
38 staa PORTB,X
12
Bi-directional I/O (Ports C and D) - Each pin of
ports C and D has an associated bit in a specific
data register and another in a data direction
register. - The primary direction of a pin is set
by its associated bit in the data direction
register. - When an output pin is read, the value
at the input to the pin driver is returned. - The
data direction registers are cleared by reset to
configure all bi-directional I/O pins
for input. - Before performing I/O operation to
these two ports, the software should set up
the data direction registers of these two ports.
13
Example 7.1 Write an instruction sequence to
output the value CD to port D. Solution REGBAS
equ 1000 PORTD equ 08 DDRD equ 09 ldx REGBAS
ldaa 3F set up the directions of port D
pins staa DDRD,X ldaa CD output CD
to port D staa PORTD,X In C language,
DDRD 0x3F / configure port D for output
/ PORTD 0xCD / output data to port D /
14
Parallel I/O Control Register (PIOC) - All
strobed mode I/O and handshake I/O are controlled
by this register
15
Strobe Input Port C - Strobe mode I/O is
selected when the bit 4 of the PIOC register is
set to 0 and port C becomes a strobe input
port. - The bit 1 of the PIOC register selects
the active edge of the STRA pin. - The active
edge of the STRA signal latches the values of the
port C pins into the PORTCL register. - Reading
the PORTC register returns the current values on
the port C pins. - Reading the PORTCL register
returns the contents of the latched
PORTCL. - When enabled, the active edge of the
STRA signal will generate an interrupt to the
68HC11.
16
Strobed Output Port B The strobe signal STRB is
pulsed for two E clock cycles each time there is
a write to port B.
17
Port C Input Handshake Protocol
- STRA is a latch command asserted by an input
device (active edge is rising in the
figure). - STRB is a ready output driven by the
68HC11 (active high in the figure). - When ready
for accepting new data, the 68HC11 asserts (or
pulses) STRB pin. - The input device places data
on input port pins and asserts the STRA signal.
The active edge of STRA latches data into the
PORTCL register, sets the STAF flag in
PIOC register and de-asserts the STRB signal.
The de-assertion of STRB inhibits external
device from strobing new data into port C. - Not
until the 68HC11 reads PORTCL, new data cannot be
applied on port C pins.
18
Port C Output Handshake Protocol
- STRA is an acknowledge input (driven by the
external device) - STRB is a ready output (driven
by the 68HC11) - In this figure, the active edge
of STRA is rising and the active level of STRB is
high. - The 68HC11 writes data into PORTCL and
then asserts STRB to indicates there are
valid data on port C pins - The external device
then asserts STRA to acknowledge the receipt of
data which will then cause STRB to be
de-asserted and the STAF flag to be set. - After
the de-assertion of STRB, STRA is also
de-asserted.
19
Simple Input Devices switches, analog-to-digital
converter, keyboards, etc. Example 6.2 Connect
an 8-DIP switch to port E of the 68HC11 and read
a byte from it.
Solution REGBAS equ 1000 PORTE equ
0A LDX REGBAS LDAA PORTE,X . . . In
C include ltstdio.hgt main () char xx xx
PORTE
20
Interfacing Parallel Ports to the Keyboard - A
keyboard is arranged as an array of switches,
which can be mechanical, membrane, capacitive,
or Hall-effect in construction. - In mechanical
switches, two metal contacts are brought together
to complete a circuit. - Mechanical switches have
a problem called contact bounce. A series of
pulses are generated because the switch
contacts do not come to rest immediately. - The
response time of the switch is several orders of
magnitude slower than that of a computer. - A
debouncing process is needed to solve the contact
bounce problem.
Keyboard input procedure Step 1. Keyboard
scanning to find out which key has been
pressed. Step 2. Key debouncing to make sure a
key was pressed. Step 3. Table lookup to find the
ASCII code of the key that has been pressed.
21

• Keyboard Scanning Techniques
• - A keyboard with more than a few keys is often
  arranged as a matrix of switches that
• uses two decoding and selecting devices to
  determine which key was pressed.
• An example of 64-key keyboard is shown in
  Figure 7.13.
• - The MC14051 is an analog multiplexor and is
  used to select the row.
• - The 74LS138 selects the column.
• - PC5-PC3 select the row and PC2-PC0 select the
  column to be scanned.
• - X7-X0 are pulled up to 5 V by the pull-up
  resistors.
• - The decoder 74LS138 outputs are asserted low.
• - A pressed key will send a low to the X output
  to the port C pin 7 and hence can be detected.

22

• Keyboard Scanning Algorithm
• The basic algorithm is shown
• in Figure 7.14.
• Since we use port C pin 0 to 2
• to select the column and pin
• 3 to 5 to select the row, we
• can use the INC PORTC,X
• instruction to move to the
• next key. This is done in the
• program on next page.

23
The program to scan the keyboard in Figure
7.13 Pins PC7 should be configured for input
while PC5-PC0 should be configured for
output. REGBAS equ 1000 base address of I/O
register block DDRC equ 07 offset of port C
data direction register from REGBAS KEYBD equ 03
port C is used as keyboard ldaa 3F set
up port C pin directions staa DDRC,X resetc
clr KEYBD,X start from row 0 and column
0 scan brclr KEYBD,X 80 debnce detect a
pressed key brset KEYBD,X 3F resetc need
to reset the row and column count inc KEYBD,X
check the next row or column bra scan end
24

• Keyboard Debouncing
• The signal output from the key switch falls
• and rises a few times within a period of
• 5 ms as the contact bounces.
• A human being cannot press and release a
• key in less than 20 ms, a debouncer will
• recognize that the switch is closed/open
• after the voltage is low/high for 10 ms.
• - Both hardware and software debouncing
• techniques are available.
• Hardware debouncing techniques
• 1. Set-reset flip-flops
• 2. Non-inverting CMOS gates
• with high-input impedance
• 3. Integrating debouncers

25
Software Debouncing Techniques The easiest
software debouncing technique is the wait-and-see
technique. After detecting a key switch has
been pressed, this technique simply wait for 10
ms and recheck the same key. REGBAS equ 1000
base address of the I/O register
block KEYBD equ 03 offset of PORTC from
REGBAS TEN_MS equ 2000 loop count for creating
10 ms delay debnce ldy REGBAS ldx TEN_MS wait
10ms nop wait for 10 ms nop dex
bne wait10ms ldaa KEYBD,X recheck the
pressed key bmi scan rescan the keyboard if
the key is not pressed jmp getcode the key
switch is indeed pressed end
26
ASCII Code Table Lookup After the key has been
debounced, the keyboard should look up the ASCII
table and send the corresponding ASCII code to
the CPU. keytab FCC 0123456789 FCC ... .
. . FCC getcode LDX REGBAS LDAB KEYBD,X
CLRA ANDB 3f compute the address of the
ASCII code of the pressed ADDD keytab key
and leave it in X XGDX LDAA 0,X get
the ASCII code END
27
Example 7.3 Write a C routine to read a character
from the keyboard. This routine will perform
keyboard scanning, debouncing, and ASCII code
lookup and return the ASCII code to the
caller. Solution char get_ascii () void
delay10ms () char tab64 . / ASCII
code table / char read_kb () char scanned,
pressed scanned 0 PORTC 0 while (1)
while (!scanned) if (PORTC 0X80) /
If key is not pressed / if ((PORTC 0x3F)
0x3F) / read row 7 and column 7
/ PORTC 0x00 / reset to row 0 column 0
/ else PORTC / scan the next key
/
28
else scanned 1 / detect a pressed key
/ delay10ms () / wait for 10 ms to
recheck the same key / if (!(PORTC
0x80)) return (get_ascii ()) / the key is
really pressed / else scanned
0 / the following subroutine use OC2
function to create a 10 ms delay / void
delay10ms () TFLG1 0x40 / clear OC2F
/ TOC2 TCNT 20000 / start an OC2
operation to create 10 ms delay / while
(!(TFLG1 0x40)) / wait until 10 ms is over
/ char get_ascii () char i i PORTC
0x3F / obtain the row and column number for
table lookup / return tabi
29
Interfacing 68HC11 with a Keypad - People are
using 12- to 24-key keypad for many
applications. - An example of 16-key membrane
keypad is shown in Figure 7.16. The row selection
is shown in Table 7.4.
30
Example 7.4 Write a C program to read a character
from the keypad shown in Figure 7.16. This
program will perform keypad scanning, debouncing,
and ASCII code lookup. Solution void wait_10ms (
) char get_key ( ) DDRC 0xF0 / configure
PC7-PC4 for output and PC3-PC0 for input
/ while (1) PORTC 0xE0 / prepare to scan
the row controlled by PC4 / if (!(PORTC
0x01)) wait_10ms ( ) if (!(PORTC
0x01)) return 0x30 / return ASCII code of 0
/ if (!(PORTC 0X02)) wait_10ms (
) if (!(PORTC 0x02)) return 0x31 /
return ASCII code of 1 /
31
if (!(PORTC 0X04)) wait_10ms ( ) if
(!(PORTC 0x04)) return 0x32 / return
ASCII code of 2 / if (!(PORTC 0X08))
wait_10ms ( ) if (!(PORTC
0x08)) return 0x33 / return ASCII code of 3
/ PORTC 0xD0 / set PC5 to low to scan
second row / if (!(PORTC 0X01))
wait_10ms ( ) if (!(PORTC
0x01)) return 0x34 / return ASCII code of 4
/ if (!(PORTC 0X02)) wait_10ms (
) if (!(PORTC 0x02)) return 0x35 /
return ASCII code of 5 /
32
if (!(PORTC 0X04)) wait_10ms ( ) if
(!(PORTC 0x04)) return 0x36 / return
ASCII code of 6 / if (!(PORTC 0X08))
wait_10ms ( ) if (!(PORTC
0x08)) return 0x37 / return ASCII code of 7
/ PORTC 0xB0 / set PC6 to low to scan
the third row / if (!(PORTC 0X01))
wait_10ms ( ) if (!(PORTC
0x01)) return 0x38 / return ASCII code of 8
/ if (!(PORTC 0X02)) wait_10ms (
) if (!(PORTC 0x02)) return 0x39 /
return ASCII code of 8 /
33
if (!(PORTC 0X04)) wait_10ms ( ) if
(!(PORTC 0x04)) return 0x41 / return
ASCII code of A / if (!(PORTC 0X08))
wait_10ms ( ) if (!(PORTC
0x08)) return 0x42 / return ASCII code of B
/ PORTC 0x70 / set PC7 to low to scan
the fourth row / if (!(PORTC 0X01))
wait_10ms ( ) if (!(PORTC
0x01)) return 0x43 / return ASCII code of C
/ if (!(PORTC 0X02)) wait_10ms (
) if (!(PORTC 0x02)) return 0x44 /
return ASCII code of D /
34
if (!(PORTC 0X04)) wait_10ms ( ) if
(!(PORTC 0x04)) return 0x45 / return
ASCII code of E / if (!(PORTC 0X08))
wait_10ms ( ) if (!(PORTC
0x08)) return 0x46 / return ASCII code of F
/
35
Simple Output Devices A Single Light-Emitting
Diode (LED) - An LED will illuminate when it is
forward biased and has enough current flowing
through it. - The current required to light an
LED brightly ranges from a few mA to more than
ten mA. - The voltage drop across a
forward-biased LED ranges from 1.7V to more
than 2 V. - The voltage drop across the LED with
10 mA current flowing through it is assumed to
be 1.7V in this chapter. - In Figure 7.17, the
74HC04 has an high output 4.9V and a low output
0.1V. A high applied to the input of 74HC04
will light the LED. - The 68HC11 does not have
the current capability to drive the LED. A chip
like the 74HC04 is needed to provide the
required current capability.
36
Example 7.5 Use the 68HC11 port B pins PB3, PB2,
PB1, and PB0 to drive blue, green, red, and
yellow LEDs. Light the blue LED for 2 s, then the
green LED for 4 s, then the red LED for 8 s, and
finally the yellow LED for 16 seconds. Repeat
this operation forever. Solution The circuit is
shown in Figure 7.18.
- To light the blue LED, output 08 to port
B. - To light the green LED, output 04 to port
B. - To light the red LED, output 02 to port
B. - To light the yellow LED, output 01 to port
B. - The required time can be created
by repeating the following delay loop for 20,
40, 80, and 160 times ldx 20000 tenth_s nop
nop dex bne tenth_s
37
regbas equ 1000 portb equ 04 org
00 lt_tab fcb 20,08,40,04,80,02,160,01 org
C000 loop ldy lt_tab next ldab 0,Y get
the repetition count ldaa 1,Y get the light
pattern iny iny ldx regbas staa
portb,X pt_lp ldx 20000 tenth_s nop nop de
x bne tenth_s decb bne pt_lp cpy
lt_tab8 reach the table end? bne
next bra loop end
The Program
38
The Seven-Segment Display - A seven-segment
display consists of seven LED segments (a, b, c,
d, e, f, and g). - A seven-segment display can be
found in common-cathode or common-anode type.
39
Driving the seven-segment displays with the
68HC11 parallel ports
- A segment requires 10 mA to be lighted
brightly. - A buffer chip like 74ALS244 can be
used to boost the 68HC11s current
capability. - The 74ALS244 has a 3V output when
it is high and a 0.2V output when it is
low. - For the circuit shown in Figure 7.20,
a segment will have a current of 13 mA when it
is lighted. - To display a BCD digit, an
appropriate value must be written to the port
register. The value is listed in Table
7.6. - When multiple digits are to be
displayed, the multiplexing technique is often
used to reduce the number of port pins required.
40
Using Multiplexing Method to Display Multiple BCD
Digits
- The 2N2222 can sink 100-300 mA of current and
can handle the maximum current (91 mA) flowing
into the collector from the common cathode. - To
light seven-segment display 5, send out the
segment pattern to port B and output the value
20 to port D. - To light display 4, send out
the segment pattern to port B and output the
value 10 to port D. - etc.
41
How the Multiplexing Method Works - To light the
display 5,,0, the corresponding value to be
written into port D are 20, 10, 08, 04,
02, and 01 respectively. For example, the
following instruction sequence will display the
digit 6 on the display 3 REGBAS equ 1000
base address of I/O register block PORTB equ 04
offset of PORTB from REGBAS PORTD equ 08
offset of PORTD from REGBAS DDRD equ 09
offset of DDRD from REGBAS six equ 7D
segment pattern of 6 third equ 08 value to
allow display 3 to light output equ 3F org
C000 ldx REGBAS ldaa output configure
port D for output staa ddrd,X ldaa six
send the segment pattern of 6 to port
B staa PORTB,X ldaa third select
display 3 to be lighted staa PORTD,X en
d
42
In C language, DDRD 0x3F PORTB
0x5F PORTD 0x08 Principle of Multiplexing
multiple displays Persistence of vision. As
long as one and only one display is lighted and
then turned off for a short period of time
within one second all digits will appear to be
lighted simultaneously.
43
Example 7.6 Display 123456 on the six
seven-segment displays shown in Figure
7.21. Solution The first step is to build a
table of segment patterns (to port B) and display
selection values (to port D).
This Table can be set up by the following
assembler directives org 00 display FCB 0
6,20 FCB 5B,10 FCB 4F,08 FCB 66,04
FCB 6D,02 FCB 7D,01
44
Algorithm for Displaying Multiple Digits Using
Time Multiplexing Technique
45
regbas equ 1000 PORTB equ 04 PORTD equ
08 DDRD equ 09 output equ 3F org
00 display fcb 06,20 fcb 5B,10 fcb
4F,08 fcb 66,04 fcb 6D,02 fcb
7D,01 org C000 ldx regbas ldaa
output staa ddrd,X forever ldy
display next ldaa 0,Y ldx regbas staa
PORTB,X
ldaa 1,Y staa PORTD,X iny iny ldx
200 loop to delay for 1 ms again nop no
p dex bne again cpy
display12 end of table? beq forever bra
next light the next display end
46
C language version include lthc11.hgt char
display 62 0x30, 0x20, 0x6D, 0x10,
0x79, 0x08, 0x33, 0x04, 0x5B, 0x02,
0x5F, 0x01 void delay_1ms ( ) main (
) int i while (1) for (i 0 i lt 6
i) PORTB displayi0 PORTD
displayi1 delay_1ms ( ) void
delay_1ms ( ) TFLG1 0x40 / clear OC2F
flag / TOC2 TCNT 2000 while (!(TFLG1
0x40))
47
Liquid Crystal Displays (LCD) - An LCD must be
activated in order to be lighted. - The LCD type
of display that is most common today allows
light to pass through it when it is
activated. - The LCD displays are organized as
segments for displaying digits or
characters. - Activation of a segment requires a
low-frequency bipolar excitation voltage of
30-1000 Hz. - When a voltage is placed
across the segment, an electric field is set up
which aligns the crystals in the liquid. This
alignment allows the light to pass through. - A
segment which is not aligned will reflect the
light. - The LCD has very high contrast and can
be seen extremely well in very bright light.
- The main problem of LCD is that it
requires light source in dim or dark area
because it produces no light of its own.
48
Optrex DMC-20434 LCD Kit - 4 ? 20 LCD kit that
uses Hitachi HD44780 as its display
controller. - Can be used with all demo boards
manufactured by Axiom Manufacturing. - DB7-DB0
are used to exchange data with the
microcontroller. - E pin is the enable signal to
the LCD. - RS selects the signal to be
accessed. - In CMD-11A8, the address B5F0 is
assigned to the control register and the address
B5F1 is assigned to data register.
49
The Setup of the DMC-20434 LCD kit - All LCD
kits need to be set up before they can be
used. - To set up the LCD kit, we need to write
appropriate commands into the command
register. - Commands for the LCD kit are listed
in table 7.8.
50
Program to initialize the DMC-20434 LCD
kit lcd_cmd EQU B5F0 lcd_init PSHX LDX lcd_c
md BRSET 0,X 80 LDAA 3C STAA 0,X set
4 ? 20 display BRSET 0,X 80 wait until LCD
is ready LDAA 01 STAA 0,X clear display
and move cursor to home BRSET 0,X 80
LDAA 0F STAA 0,X turn on
display BRSET 0,X 80 LDAA 06 STAA 0,X
set cursor increment, shift off BRSET 0,X 80
LDAA 14 STAA 0,X set cursor shift
right BRSET 0,X 80
51
LDAA 02 STAA 0,X BRSET 0,X 80
PULX RTS In C language, we need to add the
following two lines to the hc11.h file in the
ImageCraft C compiler so that we can use LCD_CMD
and LCD_DAT to access the registers of the LCD
kit define LCD_CMD (unsigned char volatile
)(0xB5F0) define LCD_DAT (unsigned char
volatile )(0xB5F1)
52
The C language version of the LCD kit
initialization function void lcd_init (
) while (LCD_CMD 0x80) / wait while LCD is
busy / LCD_CMD 0x3C / set 4 ? 20 display
/ while (LCD_CMD 0x80) LCD_CMD 0x01 /
clear display and set cursor to home / while
(LCD_CMD 0x80) LCD_CMD 0x0F / display
cursor, and cursor blink on / while (LCD_CMD
0x80) LCD_CMD 0x06 / set cursor increment,
shift off / while (LCD_CMD 0x80) LCD_CMD
0x14 / set cursor shift right / while
(LCD_CMD 0x80) LCD_CMD 0x02 / move cursor
to home / while (LCD_CMD 0x80)
53
Output Data on the DMC-20434 LCD Kit - The
DMC-20434 does not display alphanumeric data in
sequential order due to its internal line
wrapping. - Without line adjustment, the LCD kit
will display the first 20 characters in the first
line, the second 20 characters in the third
line, the third 20 characters in the second line,
and the fourth 20 characters in the fourth
line. - The following subroutine outputs one
character to the LCD kit and performs line
adjustment LCD_CMD EQU B5F0 LCD command
register address LCD_DAT EQU B5F1 LCD data
register address lcdputch2lcd STAA LCD_DAT
output 1 character to the LCD kit lcdlp LDAA LCD_C
MD read next character position BMI lcdlp
test if busy and wait if true CMPA 13 test
for line 1 wrap BEQ lcd1 if match, correct
line wrap CMPA 53 test for line 2
wrap BEQ lcd2 if match, correct line
wrap CMPA 27 test for line 3
wrap BEQ lcd3 if match , correct line
wrap RTS
54
correct line 1 wrap from line 3 to line
2 lcd1 LDAA 40 load line 2 start
position ORAA 80 set command
bit STAA LCD_CMD write to display RTS
correct line 2 wrap from line 4 to line
3 lcd2 LDAA 14 load line 3 start
position ORAA 80 set command
bit STAA LCD_CMD write to display RTS
correct line 3 wrap from line 2 to line
4 lcd3 LDAA 54 load line 4 start
position ORAA 80 set command
bit STAA LCD_CMD write to display RTS
this is the program to output a string pointed by
Y and terminated by a NULL character putstr2lcd LD
AA 0,Y BEQ done JSR putch2lcd INY BRA puts
tr2lcd done RTS

55
C Language Version of LCD Output Functions void
putch2lcd (char ch) LCD_DAT ch while
(LCD_CMD 0x80) if (LCD_CMD 0x13)
LCD_CMD 0x40 0x80 / correct line 1
wrap from line 3 to line 2 / while (LCD_CMD
0x80) if (LCD_CMD 0x53) / correct
line 2 wrap from line 4 to line 3 / LCD_CMD
0x14 0x80 while (LCD_CMD 0x80) if
(LCD_CMD 0x27) / correct line 3 wrap from
line 2 to line 4 / LCD_CMD 0x54
0x80 while (LCD_CMD 0x80)
56
void putstr2lcd (char ptr) while (ptr)
putch2lcd (ptr) ptr
57
Digital to Analog Converter - D/A conversion is
required when a digital code must be converted to
an analog signal. - A general D/A converter
consists of a network of precision resistors,
input switches, and level shifters that activate
the switches that convert a digital code to an
analog voltage or current. - D/A converters have
a fixed or variable reference voltage , which can
be generated either internally or
externally. - The reference voltage determines
the switching threshold of the precision switches
that form the impedance network that controls
the value of the output signal. - Fixed reference
D/A converts have current or voltage output
values that are proportionally to the digital
input. - Multiplying D/A converters produce an
output signal that is proportional to the product
of a varying reference level and a digital code.
58
Interfacing to the D/A Converter Using the 68HC11
Output Ports - The AD557 is an 8-bit D/A
converter that produces an output voltage
proportional to the digital input code. - The
AD557 can operate with a 5V supply. - Output
range is 0V to 2.55V when operated as shown in
Figure 6.23. - Vout (decimal equivalent of
input code) 0.01 V
59
AD557 Input latch operation - Data input can be
latched or transparent without being
latched. - The CS and CE signals together control
the latching of input data.
The AD557 can be used to generate analog
waveforms as illustrated in the next example. It
takes 1 ms to complete the conversion of one
sample.
60
Example 7.8 Use the 68HC11 port B and an AD557 to
generate a sawtooth waveform. Solution The
circuit connection is shown in Figure 7.28.
The program is in the following regbas equ
1000 PORTB equ 04 org C000 ldx
regbas clr PORTB,X again inc PORTB,X bra
again end In C language, include
lthc11.hgt main ( ) PORTB 0 while (1)
POTB
61
Example 7.9 Using the circuit in Figure 7.28 to
generate the waveform shown in Figure 7.29.
Solution REGBAS EQU 1000 PORTB EQU 04 ORG C0
00 LDY REGBAS start CLR PORTB,Y output
0V JSR delay_1ms wait for 1 ms LDAA 100
output 1 V JSR delay_1ms LDAA 200 output
2 V JSR delay_1ms BRA start
delay_1ms LDX 200 again NOP NOP DEX BNE aga
in RTS
62
The C Program to Generate the waveform shown in
Figure 7.29. include lthc11.hgt void delay_1ms (
) main ( ) while (1) PORTB 0 / output
0 V / delay_1ms ( ) / wait for 1 ms
/ PORTB 100 / output 1 V / delay_1ms (
) PORTB 200 / output 2 V / delay_1ms (
) return 0 void delay_1ms ( ) TFLG1
0x40 / clear OC2F flag / TOC2 TCNT 2000
/ start an OC2 operation with 1 ms delay
/ While (!(TFLG1 0x40)) / wait for 1 ms /
63

• Centronics Printer Interface
• Signals
• D7-D1 data pins.
• BUSY printer busy signal (output from printer)
• PE printer error (asserted high).
• SLCT printer on-line (output from printer)
• DATA STROBE An input to the printer. Data is
  latched into the printer by this signal.
• ACKNLG Printer acknowledges the receipt of
  data using this signal.

Centronics printer timing requirements
64
Interface a Centronics printer to the 68HC11 port
C

• Configure port C as follows
• 1. Set port C for output, i.e., write the value
  FF
• into DDRC.
• 2. Program PIOC to set the following parameters
• pulse mode handshake output
• no STRA interrupt
• falling edge of STRA as the active edge
• STRB is active low
• normal port C pins
• Write the value 1C into PIOC.

The timing requirements are satisfied
Data hold time (with respect to DATA STROBE) is
at least 2 E clock cycles ( 1 ms at 2 MHz).
This is greater than the 100 ns requirement.
Data setup time is period of E 2 - tPWD tDEB
325 ns gt 50 ns (required)
65
For the following subroutines, use these constant
declarations regbas equ 1000 base address
of I/O register block DDRC equ 07 offset of
DDRC from regbas PIOC equ 02 offset of PIOC
from regbas PORTCL equ 05 offset of PORTCL
from regbas PORTE equ 0A offset of PORTE
from regbas output equ FF value to set port
C as an output port Write a routine to
initialize the Centronics printer in Figure 7.32.
prt_init psha pshx ldx regbas brset
PORTE,X 40 dont go if printer
error brclr PORTE,X 80 dont go if
printer not on-line ldaa output configure
port C for output staa DDRC,X ldaa
1C initialize PIOC staa PIOC,X
pulx pula rts
66
Write subroutines to print a character and a
string using polling method The subroutine
prt_char outputs the character in
A. prt_char BRCLR PIOC,X 80 wait until
the STAF bit is set to 1 STAA PORTCL,X
print the character in A RTS The subroutine
prt_str outputs the string pointed to by index
register Y. The index register X contains the
base address of the I/O register block. The
string is terminated by a NULL character. prt_str
PSHA next LDAA 0,Y get the next
character BEQ quit is this the end of the
string? JSR prt_char print the current
character INY move the string pointer BRA
next quit PULA RTS
67
Write subroutines to print a character and a
string using interrupt-driven method prt_str1
enable the interrupt and then wait for the
printer interrupt until the whole string is
printed. prt_char1 print the character in A
and also move the string pointer Y. Set up the
interrupt vector table ORG FFF2 FDB
prt_char1 prt_str1 BSET PIOC,X 40 enable
STRA interrupt CLI again LDAA 0,Y wait
for printer interrupt BNE again is this end
of the string BCLR PIOC,X 40 disable STRA
interrupt SEI disable all interrupt RTS pr
t_char1 STAA PORTCL,X print the
character INY move the string
pointer TSX STY 5,X also update the saved
version of Y RTI
68
C Language Version of the Printer Routines void
prt_init ( ) while ((PORTE 0x40) (!(PORTE
0x80))) DDRC 0xFF PIOC 0x1C /
polling method version / void prt_char (char
ch) while (!(PIOC 0x80))) PORTCL
ch / polling method version / void prt_str
(char ptr) while(ptr) prt_char
(ptr) ptr
69
Interrupt-Driven Method Printer Routines - The
subroutine prti_str enable printer interrupt and
then stay in a wait loop to wait for
printer interrupt. - The printer interrupt
service routine (prti_char) outputs the character
pointed by Y. - The base address of I/O register
block is passed in X. - Interrupt vector table
entry for STRA interrupt must be set up
properly. prti_str BSET PIOC,X 40 enable STRA
interrupt CLI again LDAA 0,Y wait for
interrupt BNE again reach the end of the
string? BCLR PIOC,X 40 disable STRA
interrupt SEI RTS prti_char STAA PORTCL,X I
NY TSX STY 5,X update the Y value in the
stack RTI
70
C Language Version of the Interrupt-Driven
Printer Functions - The pointer to the string to
be output is defined as a global variable char
ptr void prti_str ( ) PIOC 0x40 /
enable STRA interrupt / INTR_ON ( ) while
(ptr) / wait for interrupt / PIOC
0xBF / disable STRA interrupt / INTR_OFF (
) / STRA interrupt service routine
/ pragma interrupt_handler prti_char ( ) void
prti_char () PORTCL ptr
71
The i8255 Programmable Peripheral Interface
(PPI) - In expanded mode, both port B and port C
are not available for I/O functions. - A possible
solution to this problem is to add an parallel
interface chip such as i8255 to the
68HC11. - The Intel i8255 has three 8-bit
ports port A, B, and C. - Signals A1-A0 select
the registers within the PPI as follows
72
Operation of the i8255 - When the msb is 1, the
control register defines the operation mode.
Otherwise it sets or clears a selected
bit. - i8255 has three modes mode 0, mode 1,
and mode 2.
73
Mode 0 (basic input and output) - There are two
8-bit ports and two 4-bit ports. - Any port can
be input or output. - Outputs are
latched. - Inputs are not latched. - 16 different
input/output configurations are possible in this
mode. - No handshake is required. - Data are
simply written into or read from a specified port.
74
Mode 1 (Strobed Input/Output) - Port A and B use
the lines of port C to generate or accept
handshake signals required in this
mode. - Port A, B, and C are divided into two
groups. Each group consists of one 8-bit port
and one 4-bit control/data port. The 8-bit data
port can be input or output. The 4-bit port is
used for control and status of the 8-bit data
port. - Port C pin functions are shown in Table
7.10
75
Mode 1 Input Timing - When the input buffer is
not full, the input device places data on input
port pins and pulses the STB signal. - The
falling edge of STB latches data into the input
port data register and sets the input
buffer full flip-flop. - The PPI asserts the
interrupt request signal INTR and the CPU reads
the data in the interrupt service routine. After
the data is read, the input buffer full flag is
cleared.
76
Mode 1 Output Timing - When the output buffer is
not full and the CPU is interrupted, the CPU
writes data to the i8255. For a delay of tWB
after the rising edge of the WR signal, data
appears on i8255 port pins. - The OBF signal is
asserted by the write operation. The falling edge
of the OBF latches data into the output device
and the output device asserts the ACK signal to
acknowledge the receipt of data.
77
Mode 2 (Strobed bi-directional bus I/O) - This
mode provides a means for communication with
peripheral device or structure on a single 8-bit
bus for both transmitting and receiving
data. - Only port A is used. Port A becomes an
8-bit bi-directional bus port whereas 5 bits
(PC3-PC7) of port C are used as control
port. - Functions of port C pins are shown in
Table 7.11.
78
Mode 2 Signal Transactions
79
Mode 2 Data Output Polling approach - The
software tests the OBF signal to determine
whether the output buffer is empty. If it
is, the data is written out. - The external
circuitry also monitors OBF signal to decide if
the microprocessor has sent new data to the
i8255. As soon as OBF is detected to be low, the
output device sends back the ACK signal to
remove data from the output buffer. - The low
level of the ACK signal causes the OBF signal to
go high and enables the three- state output
buffer so that data can be read. Interrupt-driven
approach - The software first enables the
i8255 interrupt. When the output buffer is empty,
it generates an interrupt to the CPU. The CPU
outputs a byte to the i8255 in the interrupt
service routine. - The byte written to the
i8255 causes the OBF signal to go low, which
informs the output device to latch data. - The
output device asserts the ACK signal to
acknowledge the receipt of data, which
causes the OBF signal to become inactive.
80
Mode 2 Data Input Polling approach - The
software tests the IBF signal to determine if
data have been strobed into the buffer. - If IBF
is low, the input device places data on port A
pins and asserts the STB signal to strobe data
into the input buffer. After this, the IBF signal
goes high. - When the user program detects that
the IBF signal is high, it reads the data from
the input buffer. The IBF signal goes low after
the data is read. Interrupt-driven
approach - The software first enables the i8255
to interrupt the CPU. - When the IBF is low, the
input device places data on the port pins and
asserts the STB signal to strobe data into the
input buffer. - After data are strobed into the
input buffer, the IBF signal is asserted and an
interrupt is generated. - The CPU reads the data
from the input buffer when executing the
interrupt service routine. - Reading data brings
the IBF signal to low, which further causes the
STB signal to go high.
81

• The i8255 on the CMD-11A8 Demo board
• - Four bytes are assigned to the i8255 on the
  CMD-11A8 demo board
• 1. B5F4 port A register
• 2. B5F5 port B register
• 3. B5F6 port C register
• 4. B5F7 control register
• Example 7.12 Configure the i8255 on the CMD-11A8
  to operate in mode 0
• Port A for input
• Port B for output
• Upper port C for input
• Lower port C for output
• Solution
• Bit 7 set to 1 to choose mode select LDX
  B5F4
• Bit 6 5 set to 0 to configure port A to mode
  0 LDAA 98
• Bit 4 set to 1 to configure port A for
  input STAA 3,X
• Bit 3 set to 1 to configure upper port C for
  input

82
Example 7.14 Use the auxiliary port of the
CMD-11A8 demo board to drive 4 seven-segment displ
ays. Use port A of the i8255 to drive the segment
pattern and use the upper four bits of port B of
the i8255 to drive the display select signals.
Write a program to display 1999. Solution - The
circuit is shown in Figure7.39. - Configure i8255
to mode 0. - Configure port A and B for
output. - Write the value 80 into the register.
83
PPI_BAS EQU B5F4 i8255 port A data register
address INIT_VAL EQU 80 value to initialize
i8255 PA EQU 0 offset of port A from
PPI_BAS PB EQU 1 offset of port B from
PPI_BAS ORG 2000 LDAA INIT_VAL forever LDY
distab next LDX PPI_BAS LDAA 0,Y STAA PA,X
send out the digit pattern LDAB 1,Y STAA PB,
X send out the select value INY INY LDX 2
00 1 ms delay again NOP NOP
DEX BNE again CPY
distab8 BEQ forever BRA next
84
distab FCB 30,08 FCB 7B,04 FCB 7B,02 F
CB 7B,01 In C language, we need to add the
following statements to the hc11.h file so that
we can use labels to reference i8255
registers define PPI_PA (unsigned char
volatile )(0xB5F4) define PPI_PB (unsigned
char volatile )(0xB5F5) define
PPI_PC (unsigned char volatile
)(0xB5F6) define PPI_CMD (unsigned char
volatile )(0xB5F7)
85
include lthc11.hgt char distab 42 0x30,
0x08, 0x7B, 0x04, ox7B, 0x02, 0x7B,
0x01 void wait_1ms ( ) main ( ) PPI_CMD
0x80 / initialize the i8255 control register
/ while (1) for (i 0 i lt 4 i)
PPI_PA distabi0 / output segment
pattern / PPI_PB distabi1 / send out
digit select / wait_1ms ( ) return
0 / create 1 ms delay / void wait_1ms (
) TFLG1 0x40 / clear OC2F flag / TOC2
TCNT 2000 while (!(TFLG1 0x40))
86
The 68HC24 Port Replacement Unit - In the early
years of the 68HC11, the amount of on-chip EPROM
or EEPROM that can be implemented onto the
microcontroller chip is very limited. - The
software of the target embedded product was to be
placed in the on-chip ROM. - During the product
development stage, software need to be modified
many times. The expanded mode must be chosen
and external EPROM must be used so that software
can be modified and tested. - Ports B and C,
which were needed in the final product, were lost
in the expanded mode during the product
development phase. - The port replacement unit
68HC24 was designed to regain ports B and C so
that the products can be evaluated and
tested. - After the design had been tested and
evaluated to be satisfactory, the software in the
external EPROM could be moved into the internal
ROM without modification as long as the
external EPROM and internal ROM occupied the same
memory space. - The signals and an example of the
68HC24 application is shown in Figure 7.38.
87
VDD
68HC11
68HC24
IRQ
IRQ
AS
AS
PB0-PB7
AD0-AD7
PC0-PC7
STRA
STRB
CS
PB3
PC0-PC7
A12-A15
PB4-PB7
E
E
R/W
R/W
RESET
RESET
from reset circuit
Figure 7.38 Circuit connecting the 68HC11 and the
68HC24