A Systematic Design Approach to Implement Interference Suppression Techniques in Wireless Communicat

1
A Systematic Design Approach to Implement
Interference Suppression Techniques in Wireless
Communications

• Ning Zhang
• Bruno Haller (Lucent Technologies)
• Bob Brodersen
• January 2000

2
Problem Statement
A
.


m

• solve to minimize
• decompose A to an unitary and an upper
  triangular matrix
• get A-1 (mn)

n

• Applications
• interference suppression and diversity combining
  for multiple antenna systems
• multi-user detection for CDMA systems
• recursive least squares filters
• any algorithm requiring matrix inversion

3
Software Implementations
all numbers are based on real matrix A of size
4x4 Cholesky decomposition only applies to
symmetric and positive definite matrix A
4
Hardware Design Methodology

• Design Space Exploration
• System level
• performance and implementation complexity
• Algorithm level
• numerical and structural properties
• Architecture level
• parallel and pipeline schemes (speed/area/energy)
• Arithmetic level
• MAC/DIV/SQRT or CORDIC
• Design Framework
• High level modeling and estimation
• Optimizations across all levels
• System/Hardware codesign

5
Module Based Approach
Algorithm
Recommendation for Modifications and
Transformations
Pre-Characterized Module Library with PDA Models
Architecture
Data Flow (construct with parameterized modules)
Control Flow
Estimation and Evaluation
(synthesize to standard cells)

(generate C code)
Netlist and Floor Plan of Macro Modules
Standard Cells
Implementation on Processor
Physical Design Information
Back-end Design flow
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Generic QRD Hardware Core

• Design parameters
• problem size (n,m)
• input rate
• fixed-point word length and iteration stages for
  CORDIC/floating-point mantissa and exponent
  length for standard arithmetic (determined by
  system level simulations)
• Parameterized building blocks
• energy/delay/area modeling
• Architectures
• 2D array with recursive CORDIC
• 1D array
• discrete mapping with pipelined array CORDIC or
  standard arithmetic
• mixed mapping with pipelined array CORDIC

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1D Discrete Mapping and Scheduling
5,5 2,3 1,4 2,2 4,5 1,3 4,4 1,2 3,5 1,1 3,4 2,5 3,
3 1,5 2,4 5,5 2,3 1,4 2,2 4,5 1,3 4,4 1,2 3,5 1,1
3,4 2,5
time
Mapping Direction
1
3
2
vectoring
rotation
Rot.
Vec.
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1D Mixed Mapping and Scheduling
4,5 2,4 4,4 2,3 1,5 2,2 1,4 3,5 1,3 3,4 1,2 3,3 1,
1 2,5 4,5 2,4 4,4 2,3 1,5 2,2 1,4 3,5 1,3 3,4 1,2
3,3 1,1 2,5
Mapping Direction
time
1
2
Rot.
Vec.
vectoring rotation
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Hardware Implementations
detection of all N data streams using Givens
rotation algorithms input rate 2MHz
estimations based on carry ripple adder