LocalityConscious Workload Assignment for ArrayBased Computations in MPSoC Architectures

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Locality-Conscious Workload Assignment for
Array-Based Computations in MPSoC Architectures

• Feihui Li and Mahmut Kandemir
• Dept. of Computer Science and Engineering
• The Pennsylvania State University
• June 14, 2005

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Outline

• Introduction
• Loop based code parallelization
• Global optimization
• Experimental evaluation
• Conclusions

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Introduction

• Why MPSoC?
• Efficient area utilization
• Easy design verification
• Flexible workload assignment
• Important issues in workload assignment
• Locality
• Parallelism
• Load balance
• Our focus improving datalocality for MPSOCs
  (mini- mizing off-chip
  references) through compiler

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Related work

• Customized memory hierarchy design and loop
  transformations for low power F. Catthoor et
  al., Kluwer Academic Publishers, 1998
• Data shackling data-centric code restructuring
  for cache based single processor system I.
  Kodukula et al., PLDI97
• Memory optimization for low power embedded
  systems W.-T. Shiue and C. Chakarabarti, DAC99
• Energy saving based on adaptive loop
  parallelization I. Kadayif et al., DAC02
• Energy efficient synchronization J.Li et al.,
  HPCA04
• Energy efficiency of CMP vs. SMT R. Sasanka et
  al., ICS04

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Loop based code parallelization
for i1,100 for j1,100

• Coarse grain parallelism loop level
• Data dependence constraints
• Parallelize each loop nest individually
• Drawback not capturing data locality between
  different loop nests

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Iteration vector and iteration space
for i1 for i2 for in

for i 1, N for j 1, N
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A motivating example
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Loop based vs. Global
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Global parallelization scheme

• Main goal improving data locality for each
  processor loop iterations accessing the same
  array region should be executed by the same
  processor
• Methodology inter-loop-nest data reuse aware
  workload assignment
• Constraint inter-loop-iteration data dependences

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Mathematical model

• Assign loop iterations to each processor based on
  array access patterns

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Issues in global parallelization

• Array element partitioning
• Array access patterns
• Cache locality for each processor
• Parallelism in the application program
• Partial array access
• A loop nest accesses a portion of the array
• Multiple arrays
• Multiple arrays accessed by the same processors
  share the same data cache
• Loop iteration mapping must consider all the
  arrays to improve data locality

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Issue-1 array element partitioning

• Use loop based parallelization to extract maximum
  parallelism
• Given iteration set Is executed by processor s,
  and the array reference function set Rs,
  determine the accessed array region
• Ds can be different for different loop nests
• A unification step to obtain a globally
  acceptable array partitioning

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A Unification example
A1000, 1000
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A Unification example
P1
L1
P2
P3
P4
Row-block array partitioning is selected
P1
P2
P3
P4
L2
P1
L3
P2
P3
P4
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Data mapping and loop iterations assignment
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Issue-2 partial array access pattern
L1 for I 10 to 300 for J 100 to 900
AI, J
L2 for I 10 to 600 for J 500 to 900
AI, J
L1
L2
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Issue-3 Multiple arrays

• Affinity two data items accessed by the same
  loop iteration are affinitive
• Affinity class a set of affinitive data elements

do t1 1, M-2 do t2 4, N Z1t1t2Z2t2t
1Z3t12t2-3
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Determining the workload of processor under
multiple arrays scenario
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An example
L1 do t1 1, N do t2 1, N
Z1t1t2Z2t2t1 L2 do t1 1,N
do t2 1, N Z1t2t1Z3t2t1
No cross-loop data dependence except for t2 in
loop nest L1
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Experimental environment

• Global optimization implemented within SUIF
• Omega library utilized to generate codes after
  loop iterations assignment
• MPSoC architecture
• 8KB L1 cache per processor
• L1 latency 2 cycles
• Main memory latency 80 cycles
• Energy values based on CACTI under 70nm technology

We thank I. Kolcu of Univ. of Manchester for
his help in implementation.
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Memory energy Improvement
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Impact of load balancing

• Load imbalance may degrade performance
• How to balance load
• Measure load imbalance severity
• Re-distribute loop iterations

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Impact of workload balancing
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Impact of data size (Conv-Spa)
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Performance improvement
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Conclusions

• A global (application wide) parallelization
  strategy for improving data locality across loop
  nests
• Data locality aware loop iterations assignment
  for MPSoC
• Experimental evaluation demonstrating the energy
  and performance improvements

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• Thank you!

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Discussion

• Obtain globally good data mapping through loop
  based parallelization and unification
• Possible negative impact on parallelism
• Expect gains from data locality outweigh losses
  in loop level parallelism

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Issue2 Array access pattern

• Problem how to partition each array such that
  iterations from the above two nests,
• , access the same
  set of elements as much as possible

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Procedure under partial array access

• Determine common elements between
• Assign the first
  to the first processor, the next
  to the second processor, and so on
• Assign other elements
  to the remaining processors
• Similar process for the second nest, except
  assigning the same set of common elements to the
  same processor as in the previous nest