Switching circuits

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Switching circuits

• Composed of switching elements called gates
  that implement logical blocks or switching
  expressions
• Positive logic convention (active high)
• High voltage or H ? Boolean 1
• Low voltage or L ? Boolean 0
• Negative logic convention (active low)
• Low voltage or L ? Boolean 1
• High voltage or H ? Boolean 0

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Switching circuits

• Logic variables ? inputs/outputs ? signals
• Signals asserted when the voltage level assumes
  the corresponding 1 value
• Positive logic asserted by H
• Negative logic asserted by L
• Logic variables are written complemented when
  they are active low
• Active high signals a, b, c
• Active low signals a, e, u

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Logic gates

• Logic gates ? switching functions
• Gate symbols two sets

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Logic gates

• Gate symbols two sets

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Logic gates

• The NAND logic function and gate

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Logic gates

• The NAND gate can be used to implement all 3
  elementary operations of switching algebra AND,
  OR, NOT

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Logic gates

• The set AND, OR, NOT implements any switching
  function (by definition) it is functionally
  complete
• Therefore, the NAND gate can be used to
  implement any switching function
• It is functionally complete, or primitive

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Logic gates

• The NOR logic function and gate

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Logic gates

• The NOR function can be used to implement all 3
  elementary operations of switching algebra AND,
  OR, NOT
• It is functionally complete too

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Logic gates

• The NOR logic function and gate

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Logic gates and equivalence

• CMOS is inverting logic
• NOR and NAND are easier to implement than OR and
  AND
• They are implemented as NOR or NAND followed by
  an inverter
• More than one representation is possible for the
  same switching function
• Different circuits of logic gates might perform
  the same switching function
• Simpler networks are preferable
• Need to analyze for equivalence and transform

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Logic gates and equivalence

• Equivalent logic networks

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Logic gates and equivalence

• Proving the equivalence

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Digital circuits

• Analysis
• Given a circuit, abstract the Boolean function it
  is implementing and try to improve the
  implementation or verify the function
• From gate diagrams
• From timing diagrams
• Synthesis
• Given a switching function, obtain the
  corresponding switching network

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Analysis

• Timing diagram

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Analysis

• Truth table

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Analysis

• Switching network

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Combinational analysis
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Signal expressions

• Multiply outF ((X Y) Z) (X Y Z)
  (X Z) (Y Z) (X Y Z)

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New circuit, same function
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Any number of manipulations can yield equivalent
circuits e.g.
F ((X Y)Z) XYZ Note XYZZ 0
(X Y)XYZ 0 (XYZ)(XYZ)
XYZ So, F (X Y) XYZZ XYZ
(X Y X)(X Y Y)(X Y Z)(Z
X)(Z Y)(Z Z) (1)(1)(X Y
Z)(X Z)(Y Z)(1) (X Y Z)(X
Z)(Y Z) Circuit
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Push bubbles to obtain cancellations
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Push bubbles to obtain cancellations
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Conclude given circuit gt many equivalent
equations circuit does not determine equation
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Also, equation does not determine circuit
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Combinational analysis given circuit, determine
function Combinational synthesis given
function, determine circuit
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Prime number detector F ? (1, 2, 3, 5, 7, 11,
13) AND-OR design
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Alarm
Derive truth table or expand A P E ? EX ?
(W ? D ? G) P E ? EX ? (W D G) P
E ? EX ? W E ? EX ? D E ? EX ? G
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A P E ? EX ? W E ? EX ? D E ? EX ?
G
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NANDs, NORs have fewer transistors than ANDs,
ORs AND-OR converts readily to NAND-NAND
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Complication if some inputs go directly to second
stage
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OR-AND to NOR-NOR
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Bubble-pushing produces non-standard
gate Solution inverters
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Bubble-pushing produces non-standard
gate Solution inverters
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Bubble-pushing produces non-standard
gate Solution inverters
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Propagation delay
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Propagation delay

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Synthesis

• SOP functions -gt AND OR networks
• POS functions -gt OR AND networks
• Not always possible to design directly
• Fan-in and out restrictions
• Most designs are modular and multi-level
• Modern designs are too complex
• Design and testing by computers
• VLSI - CAD

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Logic simulation

• Two states only for an ideal logic signal
• Two gates driving the same line in opposite
  directions
• Input left not connected or floating
• Third state X is added to the set of states
• Truth tables change

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Synthesis approaches illustrated to this point
Truth table derivation of minterms Ad hoc
construction of logic equation Need systematic
approach that minimizes hardware Karnaugh
maps Quine-McCluskey algorithm