Wireless Local Area Network Design Issues

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Wireless Local Area NetworkDesign Issues
Suchitav Khadanga
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RFIC Design Flow

• System Level Specification
• System Analysis and Architecture Choice
• Chip Set Partitioning and Chip Level
  Specification
• Preliminary RFIC Design topology Trade off
• Detailed Design Phase
• RFIC Layout
• Parasitic Extraction and Re simulation
• Fabrication
• Evaluation to Specification

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System Level Specification

• System Level Specification
• System Analysis and Architecture Choice
• Chip Set Partitioning and Chip Level
  Specification
• Preliminary RFIC Design topology Trade off
• Detailed Design Phase
• RFIC Layout
• Parasitic Extraction and Re simulation
• Fabrication
• Evaluation to Specification

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Transreceiver Architecture

• Superheterodyne Low IF down converter or Direct
  Conversion Zero IF architecture
• Synthesizer with an on chip VCO
• Separate chip for Power Amplifier

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Phase Noise of Synthesizer

• Depends primarily on the VCO
• VCO Phase noise suffers from the Low Q of on chip
  inductors
• Off chip passives can be used to improve the
  phase noise performance

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Choice of Process Technology

• CMOS
• Bi-CMOS
• SiGe
• or any other

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LAYOUT

• Impedance Mismatch
• Metal Lines are Transmission Lines

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Challenges

• Taking care of on chip parasitics
• Providing separate grounding for RF Analog and
  digital portions to avoid noise and crosstalk
  problems
• Integration of RF and Digital leads to EMI/EMC
  problems

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Thanks