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The Alpha 21264 Microprocessor

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1- 500 - 1000 MHz Clock rate. 2- Out-of-order superscalar execution ... 1- Tsunami Chipset with PTP channel instead. of regular I/O system Bus , _at_ 333 MHz ... – PowerPoint PPT presentation

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Title: The Alpha 21264 Microprocessor


1
The Alpha 21264 Microprocessor Processor Overview
Presentation By Abdullah Aldahlawi for ECE206
S01 02/13/2001
2
The Alpha 21264 Main Features
1- 500 - 1000 MHz Clock rate 2- Out-of-order
superscalar execution 3- Performance focused
instructions 4- High speed interface to memory
system 5- 64K on-chip Data Instruction
Cache 6- High speed interface to L2 cache 7-
Four Integer execution Unit, Two FP units
8- Sophisticated Branch Prediction techniques
3
The Alpha 21264
4
The Alpha 21264 -Internal Structure
1- Two Integer Clusters (2 Integer Units
Each) 2- Two FPU 3- 32 Integer Register 4-
32 FP Registers 5- Extra 48 Integer
Register 6- Extra 40 FP Register 7-
Duplicate set of 80 Integer Register 8- Branch
Predictor 9- L1 Instruction Data Cache
(64k) 10- Register Renamer
5
The Alpha 21264 Internal Design
6
The Alpha 21264 -Bus Interfaces
1- Tsunami Chipset with PTP channel instead
of regular I/O system Bus , _at_ 333 MHz -
64-Bit 2- Two Memory Banks Each has 256-Bit _at_
83 MHz Interface 3- L2 Cache Interface
128-Bit _at_ 100 MHz 4- Two Optional PCI Interface
64-Bit _at_ 33MHz
7
The Alpha 21264 Bus Interfaces
8
The Alpha 21264 Branch Prediction
1- Local Predictor - Two Level Table 2- Global
Predictor - One Table 3- Choice Predictor - One
Table
9
The Alpha 21264 Instructions Execution
1- Four Instruction are fetched and decoded from
the instruction cache 2- Instruction are assigned
to either Integer or FP Queues 3- Ready
Instruction compete for execution based on
FIFO 4- Some Instruction wait on the queue until
the become ready
10
The Alpha 21264 Pipeline Implementation
Cycle 0 - Instruction Fetch using branch
prediction Cycle 1 - Instruction data is
transferred to the register rename map hardware
Cycle 2 - Rename (map) instruction registers
Cycle 3 - Issue instructions from the queues
Cycle 4 - Read register file (Instruction
Register) Cycle 5 - Execute integer or
floating-point instructions Cycle 6 - Write
results to Dcache or Registers
11
The Alpha 21264 Microprocessor Conclusion
The 21264 Microprocessor has state of the art
technology, it delivers high performance
computing capability compared with its
competitors based on its innovative out-of-order
execution mechanism and internal design.
12
The Alpha 21264 Microprocessor
Thank you
Presentation By Abdullah Aldahlawi for ECE206
S01 02/13/2001
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