Circuit Construction

1
Circuit Construction

• Mighty Computers from Little Chips Grow

2
Compare for Equality

• What do we mean by equality?
• So for two numbers to be equal, the bit at each
  position in the first number must be identical to
  the corresponding bit in the second number

10111011 10111011
10111011 ? 10111010
3
Compare for Equality

• So if we could create a circuit which compares
  just two bits, we could join them up into a
  larger circuit which would be able to do n bits.
  Of course, n would have to be 8, 16, 32, 64, etc.

4
When are two bits equal?

• When they are both 1 or when they are both 0.

5
Each Term in Order A B
A
B
A
B
6
Each Term in Order A B
A
B
7
Each Term in Order
A

B
B
1 Bit Compare Equal (1-CE)
8
More Bits Please

• When we return to our definition of n bit equal,
  we find that two n bit values are equal only when
  each pair of bits are equal.
• This means we want to use AND because AND is only
  true when all of its inputs are true.

9
N Bit CE
a0
1-CE
b0
a1
1-CE
b1
a2
1-CE
b2
an
1-CE
bn
10
N Bit CE
a0
1-CE
b0
a1
1-CE
b1
a2
1-CE
b2
an
1-CE
bn
11
The Real World

• In real chip design, of course, these long chains
  of AND gates would take a lot of valuable chip
  space and slow things down (because wed have to
  go through each gate in turn).
• Wed look for other solutions
• Needs fewer gates
• This is called Minimization
• Ill show you a minimized circuit
• You WONT have to do Minimization

12
N Bit CE
a0
8
1-CE
b0
4
a1
1-CE
b1
2
a2
1-CE
1
b2
a3
1-CE
b3
an
1-CE
bn
13
Whats the difference?

• Suppose we have a 16 bit CE
• Original circuit has one AND for the first two
  1-CEs and one more AND for each additional 1-CE.
• This means we need 15 AND gates
• Our logic has to go through all 15 ANDs
• In our Minimized 16 bit CE
• We have one AND for each pair of 1-CEs (8)
• One AND for each pair of the previous level (4,
  then 2 then 1)
• Total AND gates is still 15
• Our logic only goes through 4 ANDs instead of 15

14
More Real World

• Its possible to build an AND gate with more than
  2 inputs
• Your Circuit simulator wont let you go more than
  3
• The q\staff\artsci\brookwellb\handouts\CircuitEdi
  tor.jar circuit editor will allow as many input
  lines as you need.
• Its a beta which means not everything (print,
  for example) works yet
• Real world components may have dozens of inputs.
• In actual Chip, wed use a 16 bit AND gate to
  connect our 1-CEs

15
N Bit CE
a0
1-CE
b0
a1
1-CE
b1
a2
1-CE
b2
a3
1-CE
b3
an
1-CE
bn
16
Binary Addition Circuit

• Everyone knows how to ADD using decimal

1 (Carry)
1 (Carry)
1 (Carry)
3 6 4 2 3 9 3
3 6 4 2 3 9 0 3
3 6 4 2 3 9 6 0 3
17
Binary Addition

• Works the same way, except you are working with
  Base-2 instead of Base-10.

1 Carry
0 Carry
1 Carry
0 0 1 1 0 1 0 0 0 1 0 1 0
0 0 1 1 0 1 0 0 0 1 0 1 1 0
0 0 1 1 0 1 0 0 0 1 0 1 0 1 0
1 Carry
0 Carry
0 Carry
0 0 1 1 0 1 0 0 0 1 0 1 0 1 0 0 1 0
0 0 1 1 0 1 0 0 0 1 0 1 0 0 1 0
0 0 1 1 0 1 0 0 0 1 0 1 1 0 0 1 0
18
Does It Work?
Binary
Decimal
1 3 5 1 8
0 0 1 1 0 1 0 0 0 1 0 1 0 1 0 0 1 0
19
Your Turn

• Add the following pairs of numbers in 8 bit
  Binary. Confirm your answer by converting them
  to Decimal and doing the math in Decimal, too.
• 00001101 00000110
• 00010110 00000010

20
The Answers
00001101 00000110 00010011
00010110 00000010 00011000
13 6 19
22 2 24
21
1 Bit Full Adder Circuit (1-ADD)

• We need to work out all possible values of our
  inputs.
• What Inputs?
• Bit from First Number (Ai)
• Bit from Second Number (Bi)
• Carry bit from previous Addition (Ci)
• What Outputs?
• Sum (Si)
• Next Carry (Ci1)

22
1-ADD
Ai
1-ADD
Inputs
Outputs
Si
Bi
Ci1
Ci
Ai 0 0 0 0 1 1 1 1
Bi 0 0 1 1 0 0 1 1
Ci 0 1 0 1 0 1 0 1
Si 0 1 1 0 ? ? ? ?
Ci1 0 0 0 1 ? ? ? ?
23
1 - ADD
Inputs
Outputs
Ai 0 0 0 0 1 1 1 1
Bi 0 0 1 1 0 0 1 1
Ci 0 1 0 1 0 1 0 1
Si 0 1 1 0 1 0 0 1
Ci1 0 0 0 1 0 1 1 1
24
Sum (Si) Ai Bi Ci Ai Bi Ci Ai Bi Ci Ai Bi
Ci
Ai
Bi
Ci
Ai
Bi
Ci
Logic Bus
VERY Important
25
Sum (Si) Ai Bi Ci Ai Bi Ci Ai Bi Ci Ai Bi
Ci
Ai
Bi
Ci
Ai
Bi
Ci
26
Sum (Si) Ai Bi Ci Ai Bi Ci Ai Bi Ci Ai Bi
Ci
Ai
Bi
Ci
Ai
Bi
Ci
27
Sum (Si) Ai Bi Ci Ai Bi Ci Ai Bi Ci Ai Bi
Ci
Ai
Bi
Ci
Ai
Bi
Ci
28
Sum (Si) Ai Bi Ci Ai Bi Ci Ai Bi Ci Ai Bi
Ci
Ai
Bi
Ci
Ai
Bi
Ci
29
Sum (Si) Ai Bi Ci Ai Bi Ci Ai Bi Ci Ai Bi
Ci
Ai
Bi
Ci
Ai
Bi
Ci
30
Sum (Si) Ai Bi Ci Ai Bi Ci Ai Bi Ci Ai Bi
Ci
Ai
Bi
Ci
Ai
Bi
Ci
31
Carry(Ci1) Ai Bi Ci Ai Bi Ci Ai Bi Ci
Ai Bi Ci
Ai
Bi
Ci
Ai
Bi
Ci
Your Turn
32
Carry(Ci1) Ai Bi Ci Ai Bi Ci Ai Bi Ci
Ai Bi Ci
Ai
Bi
Ci
Ai
Bi
Ci
33
Full Adder (1-ADD)
Ai
Bi
Ci
Ai
Bi
Ci
Si
Ci1
34
Full Adder (n Bit Add)
A
B
1-Add
1-Add
1-Add
1-Add
0
S
35
How Big Is This Really?

• Suppose we have a 32 bit computer
• Need 32 1-Add circuits
• Each 1-Add circuit is
• 3 Not
• 16 And
• 6 Or
• Not is 1 transistor / gate
• And is 2 transistors / gate
• Or is 2 transistors / gate
• Total transistors 3 1 16 2 6 2 47
• 32 47 1,504 transistors
• Minimized Optimized, the actual circuits are
  smaller (500-600 transistors)

36
So How Big is That?

• With average Transistor sizes on a Chip being
  1/10,000,00 cm2
• Area 1504/10,000,000 cm2
• Area 1.5 thousandths cm2
• Area 0.15 mm2
• Roughly .4 mm square
• Smaller than a period in on a printed page.

37
A Bit of History

• ENIAC
• One of first (Late 1940s)
• Used tubes
• 32 bit adder would be size of home freezer
• Would need cooling systems to prevent meltdown
• Would be difficult to maintain
• Best run between failures measured in MINUTES

38
Control Circuits

• Multiplexor
• Control Circuit having 2n input lines, n selector
  lines and a single output line

39
Control Circuits

• Demultiplexor
• Control Circuit having a single input line, n
  selector lines and 2n output line

40
2 Input Multiplexor
I0
O
I1
S
41
2 Input Multiplexor
I0
O
I1
S
42
Decoder

• A Control Circuit having N input lines and 2N
  output lines.
• Only one output line will have a 1
• All others are zero.

43
2 Input Decoder
I0
I1
O0
What Does the Truth Table look like?
O1
O2
O3
44
2 Input Decoder
I0 0 0 1 1
I1 0 1 0 1
O0 1 0 0 0
O1 0 1 0 0
O2 0 0 1 0
O3 0 0 0 1
45
What Are Decoders Used For?

• Decoders can be used to select the correct
  circuit.
• 00 Add
• 01 Subtract
• 10 Compare Equal
• 11 Multiply

Add
Subtract
Compare
Multiply
Instruction Number
46
7 Segment Display
a
Suppose I have a single digit (0 through 9).
From the digit, can we create a circuit which
turns on only the correct edges to display that
digit
f
b
g
c
e
d
47
What edges?
a
a
a
a
a
f
b
f
b
f
b
f
b
f
b
g
g
g
g
g
c
e
c
e
c
e
c
e
c
e
d
d
d
d
d
a
a
a
a
a
f
b
f
b
f
b
f
b
f
b
g
g
g
g
g
c
e
c
e
c
e
c
e
c
e
d
d
d
d
d
48
What Inputs?
Digit 0 1 2 3 4 5 6 7 8 9
Binary
A 0 0 0 0 0 0 0 0 1 1
B 0 0 0 0 1 1 1 1 0 0
C 0 0 1 1 0 0 1 1 0 0
D 0 1 0 1 0 1 0 1 0 1
49
What Outputs?
Digit 0 1 2 3 4 5 6 7 8 9
Binary
a
a
a
a
f
b
f
b
f
b
f
b
A 0 0 0 0 0 0 0 0 1 1
B 0 0 0 0 1 1 1 1 0 0
C 0 0 1 1 0 0 1 1 0 0
D 0 1 0 1 0 1 0 1 0 1
a 1 0 1 1 0 1 1 1 1 1
g
g
g
g
c
e
c
e
c
e
c
e
d
d
d
d
a
a
a
a
f
b
f
f
f
b
b
b
g
g
g
g
c
e
c
e
c
e
c
e
d
d
d
d
50
What Outputs?
Digit 0 1 2 3 4 5 6 7 8 9
Binary
a
a
a
a
f
b
f
b
f
b
f
b
A 0 0 0 0 0 0 0 0 1 1
B 0 0 0 0 1 1 1 1 0 0
C 0 0 1 1 0 0 1 1 0 0
D 0 1 0 1 0 1 0 1 0 1
b 1 1 1 1 1 0 0 1 1 1
g
g
g
g
c
e
c
e
c
e
c
e
d
d
d
d
a
a
a
a
f
b
f
f
f
b
b
b
g
g
g
g
c
e
c
e
c
e
c
e
d
d
d
d
a
a
f
b
f
b
g
g
c
e
c
e
d
d
51
What Outputs?
Digit 0 1 2 3 4 5 6 7 8 9
Binary
Outputs
A 0 0 0 0 0 0 0 0 1 1
B 0 0 0 0 1 1 1 1 0 0
C 0 0 1 1 0 0 1 1 0 0
D 0 1 0 1 0 1 0 1 0 1
a 1 0 1 1 0 1 1 1 1 1
b 1 1 1 1 1 0 0 1 1 1
c ? ? ? ? ? ? ? ? ? ?
d ? ? ? ? ? ? ? ? ? ?
g ? ? ? ? ? ? ? ? ? ?
f ? ? ? ? ? ? ? ? ? ?
e ? ? ? ? ? ? ? ? ? ?
52
What Outputs?
Digit 0 1 2 3 4 5 6 7 8 9
Binary
Outputs
A 0 0 0 0 0 0 0 0 1 1
B 0 0 0 0 1 1 1 1 0 0
C 0 0 1 1 0 0 1 1 0 0
D 0 1 0 1 0 1 0 1 0 1
a 1 0 1 1 0 1 1 1 1 1
b 1 1 1 1 1 0 0 1 1 1
c 1 1 0 1 1 1 1 1 1 1
d 1 0 1 1 0 1 1 0 1 0
g 0 0 1 1 1 1 1 0 1 1
f 1 0 0 0 1 1 1 0 1 1
e 1 0 1 0 0 0 1 0 1 0
53
Output a (Sum of Products)
A B C D
A B C D
A B C D
A B C D
54
Output a (Sum of Products)
A B C D
A B C D
A B C D
A B C D
55
Output a (Sum of Products)
56
Output a (A Minimization)
a A B C D A B C D
A B C D
A B C D
Use 0s instead of 1s
57
Output a (A Minimization)
a A B C D A B C D
58
Output a (A Minimization)
a A B C D A B C D