Single Inclusive Jet Cross Sections at D0

1
D? Trigger Meeting, March 15, 2001, Fermilab
L1 Tracking Digital Firmware Installation
Levan Babukhadia
SUNY at Stony Brook
http//www-d0.fnal.gov/blevan/upgrade.html
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for the CTPT DFE firmware group

• Levan Babukhadia
• Mrinmoy Bhattacharjee
• Jerry Blazey
• Brian Connolly
• Satish Dasei
• Paul Grannis
• Steve Lynn
• Manuel Martin
• Jamieson Olsen
• Ricardo Rodrigez
• Qichun Xu

3
DFE Hardware

• Platform cables in place, PS need more work, ORC
  issues, 1553/DFEC, 1month
• All DFE motherboards here and tested
• All DFEA SWDBs (808) here, testing in
  progress at PREP
• Have 5 fully tested DFEA MBs (for mid-April)
• Fully stuffed 3 CTOC and 4 CTQD DWDBs here,
  testing in progress
• Have 2 fully tested DWDBs
• 5 with problems, placement (BEST), vias, ?
• 1 CTOC and 1 CTQD DWDBs any time from BEST, fully
  stuffed in 1 week thereafter
• 1 DFEF DWDB with XCV1000E FPGAs
• Failed JTAG chain, back at BEST to reflow
• 36 XCV600 FPGAs for the remaining of CTOC, and
  CTTT, FPSS, FPTT DWDBs on order with AVNET, here
  by the end of March, fully stuffed and tested end
  of April
• 34 XCV1000E FPGAs for DFEF PO in the system, at
  AVNET by early next week, 3-4 weeks lead time,
  fully stuffed tested by end of May

4
DFE Firmware General

• Data skewed across LVDSs (out of AFEs) worse than
  expected
• ?8ns across 4(5) LVDSs out of AFE8(12), degrading
  by about ?1ns through each tier of DFE boards
  (Expected was lt ?1/4 RF cycle)
• As a result, can not remove skew across different
  DFE boards. This means that we need to
  re-synchronize in every DFE board!
• Had to significantly modify existing deskewing
  algorithm from synchronizing clocks (?1/4 RF
  cycle) to synchronizing records (?1 RF cycle)
• Synchronization of records is different for L1
  and L2. Therefore two flavors of the algorithm
  might be needed
• The L1 flavor now works in functional as well as
  in timing simulations for N links (worst case N
  10) using Virtex RAMs
• Realization that the same RAMs could be used for
  de-skew and L1 pipeline was crucial
• L3 Sender is also now implemented along with
  de-skew in L1FE (L1 Front End) module
• L1FE implemented and being tested in CTTT

5
DFE Firmware L1 FPS

• Important milestone was reached on Feb 2 the
  entire L1 FPS chain, DFEF?FPSS?FPTT successful in
  SoftBench. Next, do the same in TestStand,
  awaiting working DFEF DWDB.
• DFEF (32) Levan
• L1 done (passed TestStand)
• L2 simplified algorithm in place, need some time
  to go back and implement with proper functional
  model of Xilinx RAMs and test
• As needed, develop L2 priority reporting to
  better handle truncation, any biases
• FPSS (4) Mrinmoy
• L1 done (passed TestStand)
• Develop and implement L2 algorithm
• FPTT (1) Satish
• L1 done (passed TestStand)
• L1 ? L3 Sender nearly completed, imple-mented in
  L1FE, and L1FE in CTTT
• Need to complete L3 Record header generation,
  expect by the end of this week

FPS
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DFE Firmware L1 CFT/CPSax

• DFEA (80) Jamieson
• Track firmware done (4 FPGAs)
• Occupancy calculation nearly done
• Modifications to follow updated protocols
• Develop SoftBench (a la FPS ? Levan)
• Backend (5-th) FPGA, CPS cluster finding and
  track matching, needs more work
• CTOC (8) Brian/Ricardo
• Both L1/L2 firmware completed and tested in
  TestStand for 8 links
• Modification in Occupancy Level calculation and
  transfer protocols implemented (Brian)
• Need more extensive tests, good SoftBench
• CTTT (1) Levan/Manuel
• News now have TMO, THT1, and THT2 TTs
  implemented, what we needed by mid-April, and
  should last us long given schedule for AFEs
• Uses L1FE module, that will become front end
  firmware module in basically all DFE boards
• Expect track (TTK, TTA, TEL, TPQ, TNQ) TTs in few
  weeks
• No implementation difficulties foreseen

7
DFE Firmware L2 CTQD CPSst

• CTQD (4) Steve (new)
• Work in progress on L2CFT functionality, started
  to use RAMs instead of flip-flops, issues with
  synthesis/implementation
• Work on L2CPS has not started yet, slightly more
  complex than L2CFT
• Can not expect this sooner than a couple of
  months
• DFES (10) Qichun
• Cluster finder VHDL written and tested with-out
  4-bit cluster merging implemented yet
• Need implementation with realistic constraints,
  expect in about couple of weeks
• Develop handful of TestVectors and robust
  SoftBench, then TestStand expect in 1-2 months
• CPSS (4) Qichun
• Not started yet

8
http//www-d0.fnal.gov/blevan/upgrade.html
9
Outlook

• Hardware lagging firmware
• Because of AFE8s, ORC issues, download to DWDBs
  (DFEC), access, , can only have hit trigger in
  L1 CFT/CPSax by mid-April
• Have all digital boards for partial installation
  (5 DFEAs, 1 CTOC, 1 CTTT)
• Have L1 CTOC and now CTTT firmware, but need more
  extensive tests
• Need DFEA completion, partial, i.e. with
  occupancy count and proper protocols
• Chain SoftBench and TestStand
• Assemble chain in DAB3 and exercise firmware and
  remote operations (1553) there for the next month
  or so
• Next, need to implement full DFEA, CTOC, and CTTT
  firmware for L1 (and then for L2)
• As soon as we have working DFEF DWDB, L1 FPS
  chain TestStand (have all FPS TTs)
• Complete pieces of firmware for L2 CPSst and
  CFT/CPSax (CTQD) in a couple of months