Low Power Reconfigurable Architectures : MAIA

1
Low Power Reconfigurable Architectures MAIA

• Putting it all together..
• Vandana Prabhu ,
• Jan Rabaey
• Univ. of California, Berkeley

2
Pleiades Architecture Template

• Fixed control communication primitives
• Library of dedicated asics that is domain
  specific
• Configurable interconnect
• Dataflow driven computation
• Overall flow maintained by control processor

Configuration Bus
Communication Network
3
MAIA Architecture Control Flow
Instance for VSELP Baseband
Network
ALU
Address Generator
MAC
FPGA
. . . .
1k SRAM
IPORT
512 SRAM
OPORT
Kernel examples Dot Product, Theta
ARM8
4
System overview
EEPROM

• Off-chip Instruction/Data memory
• Intercom board for PC interface though Test Port
• Supply Voltages 2.5V(mem),1-1.2V(ARM),
  1V(Pleiades)
• Test mode to bypass ARM
• 50 MHz ExtClk frequency

MAIA
4Mb FT SyncSRAM 4.5ns cycle, 2.5V
PLEIADES
I/F
CLK GEN
TEST PORT
5
Integrating ARM8 Pleiades
TEST Pins
Wdata
32
Rdata
ConfigAdd
16
32
VAddress
32
ConfigData
32
ARM8 Core
Requests
Pleiades Reconfigurable Network
Interface
ReadData
32
Responses
Strobelt210gt
Start Requestslt90gt
Interrupt
ACKslt90gt
Off-chip SRAM
6
Interface for MAIA Configuration

• Series of memory writes to satellite
  configuration registers Interface status
  registers
• Data Mem loaded as part of configuration
• Resets network async handshaking
• Support different interrupt modes (priority,
  parallel kernels)
• Maintains state to detect end of kernel IOPort
  status
• performs SLEEP for the ARM8 core

7
Configuration overview

• Before dataflow execution
• Reset h/s, connectivity configuration modes
• Configure Address Generators, Memory, etc
• Program Interrupt Control regs to detect
  end-of-kernel
• Issue start-of-kernel requests
• Enter Sleep mode

• After dataflow execution
• Resolve interrupt priority
• AND(AGP Acks)
• OR(Port H/S)
• Interrupt(Fiq) ARM8 if allowed to
• Perform Wake-up for prior Sleep mode
• Read results from Pleiades data memory to core or
  off-chip test ports

8
Design Verification

• Design Flow
• ARM8 direct shrink from 0.6u
• MAC, SRAM Custom Asic library modules
• ALU, Interface Synthesized ASIC
• Interconnect custom
• Asynchronous H/S mixed

• Verification Strategy
• ARM8 test regression for core
• Testing of Pleiades at module level
• Validation of mem R/W by ARM from off-chip SRAM
• Validation of configuration and interrupt
  handling by ARM(including interface) using
  kernels
• Full application in VHDL system simulation

9
(No Transcript)