KILOINSTRUCTION PROCESSORS

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KILO-INSTRUCTION PROCESSORS

• Arzucan Özgür
• Department of Computer Engineering
• Bogaziçi University

15.12.2005 Cmpe 511
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Introduction
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Memory Wall
60/yr.
1000
CPU
Moores Law
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Processor-Memory Performance Gap(grows 50 /
year)
Performance
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RAM 7/yr.
RAM
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Time

• Performance improvements of high-frequency
  micro-processors is seriously limited by main
  memory access latencies

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Reducing Memory Latency
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Cache memory hierarchies

• Cache memory hierarchies
• First level (L1) cache built into the processor
  core
• Takes 1-3 processor clock cycles to access
• If there is a miss in the L1 cache ? on-chip L2
  cache accessed in the order of 10 processor
  cycles
• Accessing main memory takes at least in the order
  of 100 processor cycles
• Prefetching data from memory to the cache
• Prefetch addresses hard to predict

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Out-of-order superscalar processors
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Sequence of instructions containing data cashe
misses
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Kilo-Instruction Processors
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Definition

• An out-of-order superscalar processor that
  supports thousands of in-flight instructions
• Intelligent use of resources

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Scalability

• Thousands of In-flight Instructions and In-Order
  Commit make designs impractical
• ROB Needs to maintain a copy of every in-flight
  instruction
• IQs Instructions depending on long latency
  instructions remain in these queues for a long
  time
• LSQs Instructions remain in the queue until
  commit
• Registers A new physical register for each
  instruction producing a new value
• We would like to get the IPC of thousands of
  instructions in-flight without drastically
  increasing resource requirements

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Efficient Kilo-Instruction Processor Design

• Multi-Checkpointing the ROB
• Out-of-Order Commit
• Early Release of Resources
• Ephemeral Registers
• Load Queues

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Checkpointing
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Checkpointing

• ROB allows of the restoration of the correct
  state at any instruction (not necessary)
• Checkpoint ? a snapshot of the processor state
  taken at a specific instruction of the program
  being executed (checkpoint processor state for a
  subset of instructions)
• With this snapshot the processor can restore
  state to that point in case of an exception or
  misprediction

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Design Decisions

• How many in-flight checkpoints should be
  maintained by the processor?
• large number of checkpoints reduce the penalty of
  the recovery process
• large number of checkpoints increase the
  implementation cost
• What kind of instructions should be checkpointed?
  
• take a checkpoint at any instruction
• some instructions are better candidates (exsome
  current processors take checkpoints at branch
  instructions in order to minimize the branch
  misprediction penalty)
• How much information should be kept by each
  checkpoint?

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Multicheckpointing
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Selective Checkpointing

• Replace ROB ?? Pseudo-ROB
• Processor removes instructions that reach the
  pseudo-ROBs head at fixed rate
• Processor state is recovarable for any
  instruction in the pseudo-ROB
• Checkpoint taken when incomplete instruction
  leaves the pseudo-ROB

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Instruction Queue Management
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Bi-level Issue Queue

• Processor detects instructions that will hold an
  issue queue for a long time
• Removes this instructions from primary issue
  queue
• Offloads them to slow-lane instruction queue ?
  larger, slower, less complex
• Same principle applied to load-store queue

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Physical Register File
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Ephemeral Registers

• A conventional superscalar processor assigns
  registers to architected registers when an
  instruction enters the issue queue
• An instruction reserves a physical register for
  its entire flight time
• A physical register not written a value until
  much later ? primary function is tracking data
  dependencies
• Use virtual registers ? late register allocation
• Release register if no other instruction that
  reads the data ? early release

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Performance Evaluation
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Kilo-Instruction Multiprocessors
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Ideal Network
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References

• Adrian Cristal, Oliverio J. Santana, Francisco
  Cazorla, Marco Galluzzi, Tanausu Ramirez, Miquel
  Pericas, Mateo Valero. "Kilo-Instruction
  Processors Overcoming the Memory Wall," IEEE
  Micro, vol. 25,  no. 3,  pp. 48-57,  May/June, 
  2005.
• A. Cristal, O. Santana, M. Valero, and J.F.
  Martínez. Toward kilo-instruction processors. In
  ACM Trans. on Architecture and Code Optimization,
  Vol. 1, No. 4, Dec. 2004
• Marco Galluzzi, Valentin Puente, Adrián Cristal,
  Ramón Beivide, José-Ángel Gregorio, Mateo Valero,
  A first glance at Kilo-instruction based
  multiprocessors, Conf. Computing Frontiers 2004
  212-221

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Thank you!