GlueX electronics

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GlueX electronics

• Collaboration Meeting
• December, 2003
• Paul Smith

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• 12,500 ADC channels
• 8,200 TDC channels
• Level 1 Trigger
• 200 KHz X
• 5 KB/event
• 1GB/sec
• Digital Pipeline
• Deadtimeless

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Electronics Review

• Andy Lankford (UC Irvine) and Glenn Young (ORNL)
• at the GlueX Electronics Review - July 23 2003

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Generic Front End
Driver
Rf
Copper
Fiber
Cf
CR-(RC)n Semi-Gaussian Shaper
Pole-Zero
ADC
Pipeline
To DAQ
is
Cd
BLR
Discriminator LE, CFD, ZC
Digitization
Preamp

• Preamp parameters chosen for improved S/N, signal
  rates, power dissipation, etc.
• On-detector digitization decreases cabling
  requirements but increases complexity and imposes
  more stringent requirements on reliability.
• Copper links should be used in high radiation
  areas.

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Single channel FADC prototype
Test bed for

• SPT converter chip
• Xilinx chip and software
• Mentor PCB FPGA software
• Intellectual Property (PCI core)
• Robotic assembly

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Next (final?) version
Energy sum
Ethernet
Small Xilinx
FADC
Xilinx V2PRO
Clock/ Sync
6U
PICMG 2.16
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Cockcroft-Walton PMT base
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(No Transcript)
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Robotic Selective Assembly
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F1 TDC Block Diagram
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JLab TDC Module Top Bottom Sides
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Electronics View of Trigger/DAQ
Every 64-256 events
Trigger
Every event
Digital Pipeline
Front End Digitizer
FE/DAQ Interface
Event Block Buffers
Analog Data
To ROC
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Level 1 includes

• Forward calorimeter energy sum
• Barrel calorimeter energy sum
• Track counts
• Vertex
• Barrel
• Forward

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Photon Rates
Start _at_ 107 g/s Open and unbiased trigger Design
for 108 g/s 15 KHz events to tape
Level 1 trigger system With pipeline electronics
Software-based Level 3 System
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Selected Review Conclusions

• The decision to standardize all detector readout
  on a single TDC module design and a single Flash
  ADC module design is good, and will help simplify
  the overall electronics system design in a
  constructive way and conserve valuable
  engineering resources.
• More manpower will be needed in order to fully
  realize the GlueX electronics system.
  Considerable special (technical) expertise will
  also be required.
• The requirements and specifications of the analog
  front-end electronics are not yet adequately
  defined. This is coupled to the tentative status
  of some detector designs. The lack of full
  definition of detector designs may soon limit
  progress on electronics design,

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Integration

• Electronics racks near detector (100)
• Short cables, no extra delay
• Fiber optic connections from detector to counting
  house
• Access to detector components without uncabling

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Integration
Cerenkov
FCAL
TOF
Solenoid
Tracking