A Novel CLB Architecture to Detect and Correct SEU in SRAMbased FPGAs

1
A Novel CLB Architecture to Detect and Correct
SEU in SRAM-based FPGAs

• E. Syam Sundar Reddy
• Under the guidance of
• Dr. V. Kamakoti
• Department of Computer Science and Engineering,
• Indian Institute of Technology Madras, India

2
Single Event Upsets

• Single event upsets (SEUs) errors are circuit
  errors caused due to excess charge carriers
  induced primarily by external radiations
• These errors cause an upset event but the circuit
  it self is not damaged

3
What is LUT?

• LUT is
• - A storage block
• - Acts as a gate
• - Truth table of the gate is
• implemented
• - Can be programmed with
• any logic function
• - One-bit word

3 - input LUT
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DWC Vs Error Detection with Remap

• Proposed Technique (EDR)
• - Only one LUT
• - Find a map
• - If two o/p agree, no SEU

• Doubling With Comparison
• - Same function in 2 LUTs
• - Compare o/p of both LUTs
• - If both agree, no SEU

5
Mapping Logical Functions

• Map for (b1,b2,,bk) defined as (r1,r2,rk)
  where
• ri bj or ri bj
• 1 ? i,j ? k
• Number of possible maps for (b1,b2,,bk) is (2k)k

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Mapped function

• For a Boolean function F(b1,b2,,bk) and a map
  (r1,r2,rk), mapped function
• H (b1,b2,,bk) F(r1,r2,rk)

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Self-maps

• For none of the 4 input combinations (A,B)
  (A,B)
• - 0-self map
• For the map (B,B) of (A,B), the mapped function
  is a
• - 2-self map
• If for t of the 2k input combinations,
  (b1,b2,,bk) (r1,r2,rk) the mapped function is
  a t-self map

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Remaps and Comp-remaps

• When H (b1,b2,,bk) F(r1,r2,rk)
  F(b1,b2,,bk),
• H is a remap
• When H (b1,b2,,bk) F(r1,r2,rk)
  F(b1,b2,,bk),
• H is a comp-remap

Example of a remap
Example of a comp-remap
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SEU Detection

• The remap or comp-remap of the logical function
  stored in a LUT can be used to detect an SEU
• Goal is to find a remap or comp-remap that has 0
  self-maps, for an LUTs logical function
• Two different cells of the LUT are accessed
  simultaneously with the normal input and the
  mapped input
• Since the two cells must always agree or always
  disagree, an SEU in one of the cells can be
  detected

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Finding a remap or comp-remap

• For a 4-input function i.e., k 4, number of
  functions is
• 216 65,536 and number of maps is (2?4)4
  4096
• We tried to find a remap or comp-remap with
  minimum number of self-maps, for each of the
  65,536 4-input functions
• Unfortunately, 28 of the 4-input functions do
  not even have a remap or comp-remap
• But for each 3-input function, there exists
  either a remap or a comp-remap

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Splitting a 4-input function

• A 4-input function with no remap or comp-remap
  can be split into two 3-input functions that each
  have remaps or comp-remaps
• This allows us to propose a new CLB architecture
  where a 4-input function is split into two
  3-input functions

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New CLB architecture for SEU detection
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SEU Detection

• Configuration of the architecture consists of
  (A1,A2,A3,A4,B1,B2,B3,C1,C2,C3,M1,M2)
• A1,A2,A3,A4 are configured by the switch matrices
  whereas 8 bits are required for the remaining
  configuration
• Along with the 16 bits required for the 4-input
  function, a total of 24 configuration bits is
  required
• If there is a self-map, then the same SRAM cell
  is read by both the normal input and the mapped
  input SEU in this cell cannot be detected

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SEU correction using DWC

• Since two SRAM cell contents are read in the
  previous architecture, only one more SRAM cell is
  needed for a majority circuit
• Duplicate the LUT and use only the normal input
  of the second LUT to get a third output
• Only when a self-map occurs and the three outputs
  do not agree, a reconfiguration of the CLB is
  required

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New CLB architecture for SEU correction
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Results

• 96 of the SEU detected with out any redundancy
• Error Detection with Remaps (EDR) uses
• - 37.14 lesser area
• - 25 lesser SRAM bits than DWC
• Error Correction with Remaps (ECR) uses
• - 13.32 lesser area
• - 16.67 lesser SRAM bits than TMR