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Monolithic PhaseLocked Loops for Wideband CDMA Applications

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Monolithic Phase-Locked. Loops for Wideband CDMA Applications. Chinh Doan. Robert W. Brodersen ... Correlating filters out high frequency (fm fsymbol) phase noise ... – PowerPoint PPT presentation

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Title: Monolithic PhaseLocked Loops for Wideband CDMA Applications


1
Monolithic Phase-LockedLoops for Wideband CDMA
Applications
  • Chinh Doan
  • Robert W. Brodersen
  • University of California, Berkeley
  • BWRC Retreat
  • June 1999

2
Frequency Synthesizer Requirements
cos 2pfRFt
PN Code
RF input (fRF)
A/D
I (800 kS/s)
A/D
Q (800 kS/s)
BB Filter
Correlator
sin 2pfRFt
  • Fixed frequency for direct downconversion
  • Processing gain reduces effect of reciprocal
    mixing
  • Correlation decreases RMS phase noise

Relaxed requirements Low power, fully
integrated, CMOS implementation
3
Modeling PLL Phase Noise (Simulink)
4
Effect of Correlation on RMS Phase Noise
  • Correlating filters out high frequency (fm gt
    fsymbol) phase noise
  • Use wide bandwidth PLL to take advantage of
    correlation

5
Phase-Locked Loop Fundamentals
Phase Detector
Loop Filter
VCO
fref
fout
fdiv
N
  • Phase Detector DC value of output µ fref - fdiv
  • Loop Filter sets noise and transient performance
    of PLL
  • VCO output frequency controlled by input voltage
  • Frequency Divider fdiv fout/N

6
Phase Detector and Loop Filter
Up
ZF(s)
Ref
Vctrl
Reset
D
Dn
Q
Div
CK
Phase/Frequency Detector
Charge Pump
Active Loop Filter
  • Phase detector implemented using DCVSL to reduce
    static power and leakage current in charge pump
  • Current mismatch in charge pump is major cause of
    spurious tones
  • Fully differential, active loop filterrequired
    to minimize spurs

7
Voltage-Controlled Oscillator
Ring Oscillator
  • Large tuning range to compensate for process
    variations
  • Poor phase noise shaped by wide bandwidth PLL
  • I/Q outputs
  • Source-coupled logic levels compatible with
    Gilbert mixer

8
Frequency Dividers (HSPICE Simulations)
D
Q
D
Q
CK
CK
  • Fabricated in 0.25 mm CMOS process
  • Operates up to 3.7 GHz
  • Consumes 1.1 mW

9
Current Status and Future Work
  • Current Status
  • Fabricated low-power, high-speed frequency
    dividers
  • Simulink models of PLL to determine system level
    impairments and specifications
  • Designed and simulated VCO and PFD
  • Future Work
  • Measure performance of frequency dividers
  • Circuit design of charge pump and loop filter
  • Fabrication of complete frequency synthesizer
  • Tape out in Summer 1999
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