Pixel Ladder, PILOT Issues

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Pixel Ladder, PILOT Issues
J. Crandall, J. Hill, J. Lajoie, C. Ogilvie,
G.Tuttle, S. Skutnik

• Physical structure of first pixel layer
• FPGA-based PILOT chip readout
• Show some results from simulation model
• Kapton cable bus for parallel pixel chip readout
• Is a parallel readout structure possible?

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Implementation in PHENIX

• Pilot/control board, one per ladder
• supplies voltage to readout
• reads data from each readout
• sends data out on fiber-optic
• sets thresholds, masks etc.

start with ALICE design, modify to meet PHENIX
needs
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FPGA-based PILOT ModuleProblem Statement and
Goal

• Read 8 ALICE1 Pixel Chips in Parallel
• Keep readout time within PHENIX specification
• Minimize readout electronics
• Transmit Zero-Word Suppressed Data to Optical
  Chip (GOL)
• First look at design
• Basic functionality only
• Does it match to possible rad-hard FPGA?

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PILOT Module Block Diagram
32-bit Pixel Output _at_ 10MHz 8 chips in parallel
8 ALICE1 PIXEL CHIPS
16-bit PILOT Output _at_ 40MHz
PILOT Module
GOL
. . . . . . . . . . . . . . .
LVL1 Strobe
NEVR (Next Event Read)
CE (Chip Enable)
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PILOT Module Functional Operations

• READ
• Read 32bit-word ALICE1 Pixel Data x 256 cycles
  _at_10 MHz
• Reject zero words
• Append word/cycle Address to 32-bit data word
• (0-255)
• Store into FIFO
• WRITE
• Append Pixel Chip Address (0-7)
• Write to GOL 16-bit bus _at_ 40MHz

Full PHENIX functionality would require these two
operations to be asynchronous!
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Readout Timing

• ALICE1 Read Time
• Store 32b Pixel data 32b Address (overkill!) in
  FIFO
• Total Estimated Pixel-Chip Readout w/10 (word)
  Occupancy Zero-word Suppression
• (Note design occupancy is lt1 per channel)

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FPGA Coding

• Written in VHDL for basic functionality
• Read, Zero-suppress, Write to GOL
• Implement in FPGA Logic
• Synthesize VHDL to FPGA architecture (Xilinx)
• Implement Triple Modular Redundancy (TMR)
• TMR for state and critical logic
• Check match for size, gates, timing etc. of FPGA

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Xilinx FPGA Synthesis

• Exceeded (BRAM capacity) of XCV600E (23mm X
  23mm, 660k system gates)
• Easily fit XCV2000E (40mm X 40mm, 2M system
  gates)
• Does not currently meet ladder-physical size
  constraint, BUT
• Use a smaller die and put FIFOs in system logic.

• Device Xilinx v2000efg680-6 (40mm X 40mm)
• Number of Slices 576 out of
  19200 3
• Number of Slice Flip Flops 633 out of 38400
  1
• Number of 4 input LUTs 1001 out of 38400
  2
• Number of bonded IOBs 276 out of 516
  53
• Number of TBUFs 512 out of
  19200 2
• Number of BRAMs 32 out of
  160 20
• Number of GCLKs 2 out of
  4 50

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Functionality and Timing Tests
Simulation of read cycle and zero suppression
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Radiation Tolerance of FPGAs

• Development driven by satellite applications
• Xilinx QPro Series
• Guaranteed for 100kRad operation (9.0 rad/s
  rate)
• SEL Immunity up to LET 125 MeV cm2/mg
• SEFI Immunity up to LET 6 MeV cm2/mg (with TMR!)
• Configuration data can be scrubbed
• gt100kRad possible with self-annealing
• ACTEL Rad-Hard Antifuse (RTSX-S)
• Extensive use in industry
• SEFI LET Immunity up to 37 MeV cm2/mg (TMR in
  hardware!)
• Antifuse (program once!)
• ProASCI (Flash) not fully tested for rad-hard
  applications
• Need to more fully absorb test data and match
  PHENIX requirements

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FPGA-based PILOT Chip Future Work

• Continue with software simulation
• Multi-event readout cycle (async. READ/WRITE)
• Bit-level zero suppression, smaller headers
• Include ALICE1 and GOL behavioral models into
  simulation
• Move on to FPGA hardware, late summer/fall 03
• Implement Triple Modular Redundancy for state
  machine logic
• Radiation Dose Estimates, FPGA evaluation for
  rad-hard performance
• Evaluate failure modes, rates.

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Pixel Readout Bus
pixel chip
ladder
control

• 8 readout chips per ladder, 2 ladders laid
  end-to-end

• Multi-layered kapton
• ALICE bus 32 signal lines
• each chip read-out sequentially
• 825.6 ms 200 ms

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Line Density

• Bus width is 15mm
• Line pitch 15mm/(832) 58mm
• each output is single-ended
• Existing busses
• D0 (2001) pitch 50mm fanned out to 100mm,
• trace width 7-8mm
• D0 (2002) two // cables each with pitch 91mm
• avoided fan
• Both made by Dyconex (Swiss), other manufacturers
  identified
• Manufacturing problems scale with bus length!
• Requirements are close to state-of-the-art for
  production
• Our length (50cm), requirements not unreasonable

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Bonding Chip to Bus
wire bond density same as ALICE 12mm/32 375
mm
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Parallel Bus Summary

• Worthwhile considering what limits going to an
  832 signal bus
• allows us to read all eight chips in parallel
• time (15 ms time to write) 40 ms
• Structure of readout bus must match requirements
  and manufacturing capabilities
• Power and ground planes or traces?
• Two or four layer bus?

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Backups
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Pilot Internal Structure
L1a
NEVR
CE
READ Module
WRITE Module
To GOL
From ALICE1
Count_ enable
cout
addr
8b-Counter
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Read Module FIFO (Parallel Operation,
Replicated 8x)
L1a
Read Control LogicX
64b Data_in
From ALICE1
64b X 256 deep FIFOX (Synchronous)
64b Data_out
Rd_enable
NEVR
CE
Wr_enable
Count_enable
addr
cout
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FIFO Write Module (Daisy-Chain Operation,
Replicated 8x)
Done x-1
Startx
L1a
64b X 256 deep FIFOX (Synchronous)
64b Data_out
Write Control LogicX
empty
16b to MUX
Wr_enable
Donex
Start x1
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Write Daisy Chain
FIFO x-1
WRITE x-1
GOL
MUX
FIFO x
WRITE x
FIFO x1
WRITE x1
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