Outline

1
Effects of Global Interconnect Optimizations on
Performance Estimation of Deep Sub-Micron Design
Yu Cao, Chenming Hu, Xuejue Huang, Andrew B.
Kahng, Sudhakar Muddu, Dirk Stroobandt, Dennis
Sylvester
2
Outline

• Introduction
• Study implementation
• Global interconnect optimization issues
• Inductance effect
• Wire sizing
• Repeater insertion
• Via parasitics
• Conclusions

3
Performance Prediction

• Performance estimated from critical path analysis
• Previous prediction assumes
• RC line model for interconnect delay
• Optimal repeater sizing and ideal placement
• Switch factor bounded by 0,2
• Design constraints excluded, such as noise
  margin, delay uncertainty and area cost
• Via resistance from buffer insertion neglected

4
Study Implementation

• GSRC Technology Extrapolation (GTX) Engine as
  study framework
• http//vlsicad.cs.ucla.edu/GSRC/GTX
• Typical 0.18µm device technology and 15mm copper
  global interconnect, line thickness1.3µm

5
Inductance Effect on Line Delay

• Line behavior is RLC dominant when b12-4b2lt0,
• where b1RsCRsCLRCL, b2RsC2/6RsRCCL/2RC2/24
  R2CCL/6LCLCL

6
Shielding Technology
One Side Shielding (1S)
Two Side Shielding (1S)
No Shielding (NS)
Vdd/GND Lines
Signal Lines

• Shielding is helpful to define the current return
  path for inductance coupling and to reduce
  crosstalk noise
• Cost Signal wire pitch x Repeater sizing factor
  x Number of repeaters

7
Shielding Cost Optimization

• Variables for cost optimization repeater size,
  number of repeaters, wire width and spacing
• Cost Optimization Constrains Line Delay lt 1ns
  Noise peak lt 20 Vdd Transition time lt 500ps
  Delay uncertainty (?)
• Ignoring inductance can overestimate chip cost
  (gt20)

8
Wire Size Optimization

• Formula Wopt(l)Rin(Cfl2CL)/(2RDCa)1/2
• Formula has up to 30 error from RLC model
• J. Cong and D.Z. Pan, Interconnect Estimation
  and Planning for Deep Submicron Designs, Proc.
  DAC, 1999, pp. 507-510

9
Repeater Size Optimization

• Bakoglu sizing SRDCint/(RintCin)1/2
• Simple sizing expression overestimates optimal
  repeater size

10
Repeater Placement Uncertainty
Lseg
Lseg
eLseg

• Repeater placement uncertainty e has a large
  impact on peak noise (up to gt70) but little
  impact on delay (lt5)

11
Staggered Insertion of Repeaters
Normal (non-staggered) Repeater Insertion
Staggered Repeater Insertion

• Staggered insertion significantly reduces peak
  noise and almost eliminates delay uncertainty
• A. B. Kahng, S. Muddu, and E. Sato, Tuning
  Strategies for Global Interconnects in
  High-Performance Deep Submicron ICs, VLSI
  Design 10(1), 1999, pp. 21-34

12
Via Parasitics

• Via resistance is 47O/via for 0.18µm technology
  (signal line resistance is about 20O/mm)
• Ignoring via parasitic resistance can introduce
  10-20 underestimation of delay
• In the future more metal levels will causes
  larger via resistance but copper technology can
  significantly reduce it

13
Conclusions

• Analytical models need to be carefully applied on
  line delay and noise estimation
• Conventional models may lead to large error in
  optimal sizing
• Realistic conditions (layout uncertainty, via
  parasitics, shielding case, etc.) are important
  for correct prediction
• GTX can be a powerful tool for quantified
  prediction