4-bit Shift Register using Xilinx XST and FPGA

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4-bit Shift Register using Xilinx XST and FPGA

• EE102 Lab
• Winter 2005
• Electrical Engineering and Computer Science
• Ohio University

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Outline

• 4-bit shift register
• Prototype system Spartan-3
• Sample design overview
• Lab Procedure
• Testing
• Schedule

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4-bit shift register
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Prototype system Spartan-3
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Sample design overview

• 4-bit shift register
• Reset button Btn0
• Preset button Btn1
• Clock button Btn2
• Input bit switch 7
• Preset data switch 3-0

• Three functional modules
• 4-bit shift register
• Controller controlling the state of reset, load
  or shift
• I/O interface

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Procedure
1. Creating project and adding source
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Procedure
2. Creating one-bit register symbol
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Procedure
3. Building 4-bit shift register in Schematic
Editor
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Procedure
3. Building 4-bit shift register in Schematic
Editor
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Procedure
3. Building 4-bit shift register in Schematic
Editor
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Procedure
4. Adding design constraints
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Procedure
5. Synthesize the design
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Procedure
6. Generate the bit programming file
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Procedure
7. Download the bit file to FPGA chip
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Procedure
8. Test the design
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Schedule

• Webpage
• http//www.ent.ohiou.edu/webcad/ee102
• Please print out the instruction before the lab
• Schedule
• A01   03/08 Tuesday 1PM3PAM 
• A02 03/10 Thursday 8AM10AM
• A03 03/10 Thursday 1PM3PM
• Rm 306, Stocker Center

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Thank you
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HDL(Hardware description language)

• VHDL Very high-speed integrated circuits
  Hardware Description Language a higher level of
  abstraction to capture designs.
• Xilinx XST Xilinx Synthesis Tools take these
  HDLs and automatically translate them into
  schematics, map them as gates and switches on
  FPGA chip.