SelfBiased, HighBandwidth, LowJitter 1to4096 Multiplier Clock Generator PLL

1
Self-Biased, High-Bandwidth, Low-Jitter 1-to-4096
Multiplier Clock Generator PLL

• Based on a presentation by
• John G. Maneatis1, Jaeha Kim1, Iain
  McClatchie1,Jay Maxey2, Manjusha Shankaradas2
• True Circuits, Los Altos, CA1
• Texas Instruments, Dallas, TX2

PDF file of JSSC paper linked at class web page.
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Clock Generator PLLs for ASICs

• Most ASICs PLLs for clock generation, but
• Use different frequencies and multiplication

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Optimal PLL Design

• For each FOUT and N, one must adjust loop
  parameters for both minimum jitter and stability
• For clock generators (track input clocks) (wREF
  2pFOUT/N)
• Loop bandwidth wN wREF/20
• Damping ratio z 1
• Third-order pole wC wREF/2
• Circuit parameters (e.g. ICH, R) must vary with
  FOUT and N!

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Addressing Diverse Specifications

• Designing a different PLL for each ASIC
• Easier to meet the specification, but
• Verifying all designs is difficult and costly
• Our Goal One PLL design for all ASICs
• Only one design needs verification, but
• Loop parameters must adjust automaticallyto
  satisfy wide range of FOUT and N

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Challenges

• Self-biased PLLs Maneatis 96 adjust for FOUT
• Achieve fixed wN/wREF and z indep. of PVT
• But, Self-Biased PLLs do NOT adjust for N
• wN/wREF and z vary with N (want fixed)
• wC/wREF varies with N (want fixed)
• This talk extends Self-Biased PLLs for wide
  ranges of N with a new loop filter network

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Outline

• Introduction
• Review of Self-Biased PLLs
• Pattern Jitter Issues
• Loop Filter Architecture
• Implementation of Key Circuits
• Measured Results
• Conclusions

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Second-Order PLLs

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Second-Order PLLs

Oscillation frequency is supposed to be
controlled by VCTL, that is by ICH/CS ICHR. In
Ring Oscillators, frequency is more easily
controlled by current, through tail biasing
voltage. ? want tail current to have two
components ICH/CS ICHR.
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Self-Biased PLLs
VBN biases the tail current in Ring Oscillator
buffer stages.
So want ID to have components
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Self-Biased PLLs
Op Amp adjust VBN so that NMOST ID matches
currents in 1/gm and that from top charge
pump. Notice VCTL VDD ICH / sC1 d ID (VDD
VCTL)gm ICH-ff ICH (1/sC1 1)
Hence VBN will generate I-tail proportional to
ICH (1/sC1 1)
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Maneatis self bias generator
From 1996 Maneatis paper, which is very widely
reference. PDF file linked at web page.
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Self-Biased PLLs

• With Self-Biased PLLs
• wN/wREF and z are constant with FOUT,BUT not
  with N

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Pattern Jitter / Spurious Noise

• Phase corrections every rising reference edge can
  cause disruptions to nearby output cycles
• Periodic noise pattern repeats every ref. cycle
  or N output cycles
• Typical causes
• Charge pump imbalances or leakage
• Jitter in reference clock (aperiodic result)

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Shunt Capacitor

• Use third-order pole to extend disturbance with
  reduced amplitude over many output cycles
• Problem with varying N using fixed capacitor
• Extended number of cycles NOT function of N
• Too few for large N ? Pattern jitter
• Too many for small N ? Instability

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Proposed Loop Filter

• Use switched capacitor filter network to
• Output scaled amplitude error signal with N
  output cycle duration Maxim 01
• Want a simple solution using this approach that
  is compatible with Self-Biased PLLs

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Original Filter Network

• Only need to filter feed-forward path

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Sampled Feed-Forward Network

• Sample phase error and generate proportional
  current that is held constant for NTOUT
• Sampled error is reset at end of ref. cycle
• Need VRST VCTL as zero bias level

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Complete Filter Network

• Reset C2 to VCTL directly
• Eliminates C1 charge pump
• Equivalent feed-forward control gain
• QO N QI

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Loop Dynamics

• With this new loop filter network we achieve
• Need to keep wN/wREF and z constant with N
• Just scale charge pump current with 1/N (x)
• More detailed analysis will show
• Both are independent of FOUT, N, and PVT!

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Complete Self-Biased CGPLL

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Self-Biased Filter Network

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Filter Network Reset Switches

• Can switch to VCTL independent of voltage level

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Filter Network Reset Switches
D
C
A
B

• When un-selected, sel 0, sel_B 1 (VDD). V_B
  VDD, V_D VDD V_CTL, V_A 0, V_C V_BR
  V_CTL.
• V_CA charged to V_CTL

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Filter Network Reset Switches
D
C
A
B

• When selected, sel_B 0, sel 1 (VDD). V_A
  VDD, V_C VDD V_CTL, V_B 0, V_D V_BR.
• V_DB charged to V_BR or V_CTL

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Inverse-Linear Current Mirror

• Need to generate ICH ID / N
• Use switches to adjust device size on input side
• For N14096, need 12 binary weighted legs
• Need size range of 20481 ? Too much area!

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Multi-Stage Linear CM

• Solution to size problem with LINEAR control
• Use multiple device groups operating at different
  but ratioed current densities
• Can have large ranges using small devices

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Multi-Stage Inverse-Linear CM

• Just diode connect multi-stage linear current
  source and use as input side of current mirror
• Can output gate bias of any device group
• Stable as long as gain blocks reduce currents

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Complete Current Mirror

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Voltage-Controlled Oscillator

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Buffer Tail Node Matching

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Modified VCO

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Static Supply Sensitivity

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PLL Implementation

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Measured Jitter vs N (240MHz)

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PLL Jitter Measurement Summary
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Conclusions

• Proposed PLL achieves wide N and FOUT range
• PLL is self-biased with constant loop dynamics
  (wN/wREF, z ), independent of N, FOUT , and PVT
• Sampled feed-forward network suppresses pattern
  jitter with effective wC that tracks wREF
• Achieves relatively constant period jitter of
  less than 1.7 as N is scaled from 1 to 4096

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References

• J. Maneatis et al., Self-biased high-bandwidth
  low-jitter 1-to-4096 multiplier clock generator
  PLL, in IEEE Int. Solid-State Circuits Conf.
  Dig. Tech. Papers, Feb. 2003, pp. 424425.
• J. Maneatis, Low-jitter process-independent DLL
  and PLL based on self-biased techniques, IEEE J.
  Solid-State Circuits, vol. 31, pp. 17231732,
  Nov. 1996.
• A. Maxim et al., A low-jitter 1251250 MHz
  process-independent 0.18 m CMOS PLL based on a
  sample-reset loop filter, in IEEE Int.
  Solid-State Circuits Conf. Dig. Tech. Papers,
  Feb. 2001, pp. 394395.
• T. C. Lee and B. Razavi, A stabilization
  technique for phase-locked frequency
  synthesizers, in Symp. VLSI Circuits Dig. Tech.
  Papers, June 2001, pp. 3942.
• J. Maneatis and M. Horowitz, Precise delay
  generation using coupled oscillators, IEEE J.
  Solid-State Circuits, vol. 28, pp. 12731282,
  Dec. 1993.