Power Issues in VLSI Design

1
Power Issues in VLSI Design

• By
• Venkat Rao
• Gaurav Singhal

2
Outline of the talk

• CMOS Energy and Power Why is it an issue?
• Clock Gating.
• Dynamic Voltage Scaling.
• Dynamic Power Management.
• Battery Awareness.

3
CMOS Energy and Power

• E CL VDD2 P0?1 tsc VDD Ipeak P0/1?1/0 VDD
  Ileak/f
• P CL VDD2 f tscVDD Ipeak f
  VDD Ileak

f P fclock
Dynamic power (80 today and decreasing
relatively)
Short-circuit power (5 today and decreasing
absolutely)
Leakage power (15 today and increasing)
4
Dynamic Energy Consumption
Vdd
Vin
Vout
CL
Energy/transition CL VDD2 P0?1
5
Scaling is worsening the problem
100000
10000
1000
Pentium
Power (Watts)
100
286
486
10
8086
386
8080
8008
8085
1
4004
0.1
1971
1974
1978
1985
1992
2000
2004
2008
Power delivery and dissipation will be
prohibitive !
Source Borkar, De Intel?
6
Power Density will Increase
10000
1000
100
Power Density (W/cm2)
8086
10
8008
Pentium
8085
4004
386
286
486
8080
1
1970
1980
1990
2000
2010
Power densities too high to keep junctions at low
temps
Source Borkar, De Intel?
7
Leakage Power
Vout
Drain junction leakage
OFF
Sub-threshold current
Gate leakage
Independent of switching
8
Leakage Current
9
Scaling worsens leakage power
Drain leakage increases as VT decreases to meet
frequency demands leading to excessive leakage
power.
8KW
50
100,000
50nm
1.7KW
40
10,000
70nm
30
400W
100nm
Drain Leakage Power
Ioff (na/nm)
1,000
130nm
88W
20
12W
100
180nm
10
10
0
30
40
50
60
70
80
90
100
2000
2002
2004
2006
2008
Temp (C)
Source Borkar, Intel?
10
Power versus Energy
Watts
Lower power design could simply be slower
time
Watts
Two approaches require the same energy
time
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Outline of the talk

• CMOS Energy and Power Why is it an issue?
• Clock Gating.
• Dynamic Voltage Scaling.
• Dynamic Power Management.
• Battery Awareness.

12
Clock Gating
Most popular method for power reduction of
clock signals and functional units
R e g
Functional unit
clock
disable
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Gated Clock Distribution
If the paths are perfectly balanced, clock skew
is zero
Can insert clock gating at multiple levels in
clock tree Can shut off entire subtree if all
gating conditions are satisfied
Clock
disable
gated clock
clock
H-Tree Clock Network
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Clock Gating Levels

• Fine-grain
• E.g., portions of the pipeline register are
  disabled depending on whether the information
  they hold is used in the next stages
• Medium-grain
• E.g., disable cache precharging during cache miss
• Coarse-grain
• E.g., eliminate switching of the clocks main
  driver

Higher recovery overhead
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Reducing Leakage

• Static power in off-state is a serious concern
  in nanometer technologies
• Techniques tradeoff leakage reduction for ease of
  recovery from shutdown
• Most of the techniques have non-negligible
  recovery cost
• Dual-mode CT model does not hold!

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I. Input Vector Control

• Transistor Stack Effect the leakage reduction
  effect in a transistor stack when more than one
  transistor is turned off.

A simple 2-input NAND gate
D
G
S
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II. Supply Gating

• Gating the Power Supply
• The power supply is shut down so that idle units
  do not consume leakage power
• If there is intention to provide support for
  Dynamic Voltage Scaling (DVS)
• Switching regulators
• On-chip voltage generators (PLL)

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Power Supply Switching

• Requires re-stabilization of Vdd
• Significant time and power cost

Switching DC-DC regulator
OSC Duty Cycle Control
Vdd
LC Low Pass

-
Vset
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Outline of the talk

• CMOS Energy and Power Why is it an issue?
• Clock Gating.
• Dynamic Voltage Scaling.
• Battery Awareness.

20
Exploiting Variable Supply

• Supply voltage can be dynamically changed during
  system operation
• Cubic power savings
• Circuit slowdown
• Just-in-time computation
• Stretch execution time up to the max tolerable

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Variable-supply Architectures

• High-efficiency adjustable DC-DC converter
• Adjustable synchronization
• Variable-frequency clock generator
  Chandrakasan96
• Self-timed circuits Nielsen94

SoC
Workload Predictor
Clkgen
Vdd
Switching DCDC regulator
WK to f
f to Vdd
Vset
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Basic problem formulation

• Given a task, with known WCET and deadline d
• Find the optimal voltage for the processor that
  runs it (minimize energy without violating d)

Vdd(S)
WCET
sl
Vmax
d
VT
ST(WCETsl)/WCET S1/(Utilization)
S
ST
1
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Accounting for limited (f,Vdd) resolution
Task Energy

• Frequency interpolation
• Given a task with N operations
• Compute optimum (fideal,Vdd,ideal)
• Find the two closest available frequencies
• fLltfidealltfH
• Run for X at fL and (N-X) at fH
• Nfideal XfL (N-X)fH

The task executes all its N cycles at V1 E NEV1
The task executes partly at V2 and partly at
V3 E xEV2 (N-x)EV3
Task Execution Time
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Intel Xscale Supports DVS

• Transition penalties
• Dominated by supply voltage transient
• 1mV/2µsec

From Intels Web Site
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Outline of the talk

• CMOS Energy and Power Why is it an issue?
• Clock Gating.
• Dynamic Voltage Scaling.
• Battery Awareness.

26
Battery Awareness

• The traditional algorithms on DVS considers
  battery as an ideal power source, i.e. energy
  delivered by the battery is constant under
  varying conditions of voltages and currents.

Battery is a Non ideal Source of energy!!
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Battery is Important!!

• Battery behaviour is very complex which is the
  result of complex electro-chemical reactions
  inside battery.
• Energy/charge delivered by the battery is
  dependent on discharge profile (voltages and
  currents).
• An accurate battery model is required.

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Battery Life Modeling
effect
- effect
Recovery Effect

• Rate Capacity Effect

Shelf Life Effect
Temperature Effect
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Summary

• Power is becoming the restraining factor in
  further miniaturization and scaling.
• Various methodologies available but still a lot
  of scope for improvement.
• Need for developing of infrastructure.
• Combining of discrete power saving techniques
  into a single integrated system.

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• Rate Capacity effect -gt Battery efficiency
  decreases with increase in current.
• Recover effect -gt Battery tends to recover some
  charge if even rest periods.

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• THANK YOU