Lecture 3: MIPS 2000 Instructions Part 1

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Lecture 3MIPS 2000 Instructions (Part 1)

• ECE 201-11
• 27 Jan 04

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Administration

• Web Page will be migrating to Blackboard later
  this week
• Questions?

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Programming Levels of Representation
temp vk vk vk1 vk1 temp
High Level Language Program
Compiler

• lw 15, 0(2)
• lw 16, 4(2)
• sw 16, 0(2)
• sw 15, 4(2)

Assembly Language Program
Assembler
0000 1001 1100 0110 1010 1111 0101 1000 1010 1111
0101 1000 0000 1001 1100 0110 1100 0110 1010
1111 0101 1000 0000 1001 0101 1000 0000 1001
1100 0110 1010 1111
Machine Language Program
Machine Interpretation
Control Signal Specification
ALUOP03 lt InstReg911 MASK

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Computer Instructions

• Instructions are the words used by a computer
• The instruction set is the computers vocabulary
• MIPS is the instruction set used throughout PH,
  and which we will study in this course
• We will examine both the MIPS assembly and
  machine code languages

00000000010000010001100000100000
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Generic Examples of Instruction Format Widths

Variable Fixed Hybrid
Variable Fixed Hybrid

What are the advantages and disadvantages of each
type of format?
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MIPS Architecture Registers and Memory
r0

• The MIPS architecture is considered to be a
  typical RISC architecture.
• Simplified instruction set gt easier to study
• Most new machines are RISC
• Programmable storage
• 32 x 32-bit GPRs (r0 0)
• special purpose - HI, LO, PC
• 32 x 32-bit FP regs
• 232 x bytes of memory
• Memory is byte addressable
• Words are 32 bits 4 bytes
• Words start at multiple of 4 address

r1
r31
PC
lo
hi
f0
f1
f31
000000
000100
001000
111000
32 bits
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Registers

• Registers are at the top of the memory hierarchy
  in computer hardware design
• All data must be represented in a register before
  it can be processed
• Onboard the processor
• Smaller is Faster
• In MIPS, register size is 32 bits. This
  corresponds to the instruction or word size for
  the instruction set
• Visible to the programmer
• MIPS convention when addressing register is 2
  characters following a sign e.g. s1

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Register Names in MIPS Assembly
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MIPS Assembly add Instruction

• Addition in MIPS assembly follows the following
  format
• dest source 2
• add s0, s1, s2
• source 1
• This is equivalent to the following higher level
  code
• a bc
• where variables a, b, and c are already located
  in registers s0, s1, s2, respectively
• This same format is used by sub (the subtraction
  instruction) and many other (not all) R-type
  instructions

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Example of Using MIPS Instructions - Variables

• The compiler translates high-level code to
  assembly language.
• Variables are typically stored in registers - why
  ?
• Replace the C code for
• a (b c) - (d c)
• by equivalent MIPS instructions.
• Assume the variables a, b, c, and d are in
  registers s3, s4, s5, and s6, respectively.
• Instruction Comment .
• add t2, s5, s6 t2 b c
• add t3, s4, s6 t3 d c
• sub s3, t2, t3 a t2 - t3

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MIPS Instruction Fields R-Type Instructions

• add and sub are examples of Register type
  (R-type) instructions.
• R-type instructions have the following machine
  code format

R-type
Field Meaning op Basic operation of the
instruction (opcode) rs First register source
operand rt Second register source
operand rd Register destination operand (gets
result) shamt Shift amount funct Function field
- selects the variant of the operation in the
op field (function code)
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Translating MIPS Assembly into Machine Language

• Humans see instructions as words (assembly
  language), but the computer sees them as ones and
  zeros (machine language).
• The assembler translates from assembly language
  to machine language.
• For example, the MIPS instruction add t0, s1,
  s2 is translated as follows (see back of book)
• Assembly Comment
• add op 0, shamt 0, funct 32
• t0 rd 8
• s1 rs 17
• s2 rt 18

00000
100000
01000
10010
10001
000000
funct
shamt
rd
rt
rs
op
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MIPS Instruction Fields I-Type Instructions

• addi is an example of an Immediate type (R-type)
  instruction.
• I-type instructions have the following machine
  code format

I-type
immed
rt
rs
op
6 bits 5 bits 5 bits 16 bits
Field Meaning op Basic operation of the
instruction (opcode) rs First register source
operand rt Register destination operand (gets
result) immed Immediate value or address
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I-Type Example

• Compile and assemble into MIPS the following
  higher level pseudo code
• a 2(bc) 100
• Assume that b and c are located in registers s2
  and s3, respectively.

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Transferring Data to/from Memory

• Recall that all data must be represented in a
  register before it can be processed.
• MIPS is an example of a load-store architecture.
  Data (and instructions) must be loaded from
  memory into a register, and stored from the
  register back into memory.
• The corresponding instructions are lw (for load
  word) and sw (for store word)
• lw and sw are I-type instructions where the
  source register contains a based address in
  memory and the immediate the address offset.

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Transferring Data to/from Memory (contd)

• Example lw t0, 100(s1)
• Words in MIPS must always start at addresses that
  are multiples of 4.

35 17 8
100
immed
rt
rs
op
s1100 s1
100011100
Main Memory
100011100
Registers
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Examples

• Provide the MIPS assembly code for the following
• g h A10
• where the base address of the word array A, g,
  and h are located in registers s1, s2, and t1,
  respectively
• lw t0, 40(s1) t0 A10
• add s2, s1, t0 s2 s1t0
• How about the assembly code for the following
• A2 A0 A1

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Transferring Data to/from Memory (contd)

• addi accommodates adding 16-bit constants to a
  register, but how do we handle 32-bit constant
  additions?
• This can be accomplished using the lui
  instruction (load upper immediate)
• lui t0, 255
• which in this example loads the immediate value
  255 into the upper 16 bits of register t0, and
  fills the lower 16 bits with 0s. i.e.
• t0 0000 0000 1111 1111 0000 0000 0000 0000
• Example Load the following 32-bit constant to
  register s0.
• 0000 0000 0011 0000 0000 0000 1000 1111
• lui s0, 48
• addi s0, 143

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MIPS Instructions Conditional Statements

• Conditional statements allow us to make decisions
• MIPS provides 2 I-type assembly instructions that
  are equivalent to an if statement with a goto
• beq reg1, reg2, L1 if reg1reg2 goto label L1
• bne reg1, reg2, L1 if reg1 ! reg2 goto label
  L1
• Example if (ij) goto L1
• f gh
• L1 f f-i
• Assuming that f, g, h, i, j are in registers
  s0-s4, the equivalent MIPS code would be
• beq s3, s4, L1
• add s0, s2, s2
• L1 sub s0, s0, s3

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Unconditional Branch

• What if we had wanted an if-then-else statement
• MIPS supports a jump instruction to address this.
  
• j Exit
• jumps to the position in memory where the label
  Exit is located
• j is an example of an Jump type (J-type)
  instruction.
• J-type instructions have the following machine
  code format

J-type
op
target address
6 bits 26 bits
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if-then-else example using j
Again, assuming that f, g, h, i, j are in
registers s0-s4, the equivalent MIPS code would
be? C Code MIPS Assembly if (ij) bne
s3, s2, else f gh add s0, s1,
s2 else j Exit f
f-i Else sub s0, s0, s3 Exit
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Compiling a while loop
Lets implement the following while loop?
Associate the variables i,j,k with registers
s0-s2, and the base address for the array A with
s3 C Code MIPS Assembly i 0 add
s0, zero, zero while (i!j) add t0,
s3, zero Ai i Loop beq s0, s1,
Exit i sw s0, 0(t0)
addi s0, 1 addi t0, 4 j
Loop Exit
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Comparison Operations

• Inequality checks make for the basis of many loop
  tests
• MIPS implements this with the slt or set on less
  than instruction
• slt t0, s1, s2
• In the above example, t0 will be set to 1 if the
  value of s1lts2. Otherwise, t0 is set to 0.
• The corresponding immediate version of this
  instruction is
• slti t0, s1, 100
• slt is an R-type instruction, whereas slti is an
  I-type

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Compiling a for loop
Lets compile the following for loop? Associate
the variables i,j,k with registers s0-s2, and
the base address for the array A with s3 C
Code MIPS Assembly??? k 0 for(i0
iltj i) k k Ai
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MIPS Addressing Modes

• Addressing modes specify where the data used by
  an instruction is located.
• Mode Example Action
  .
• Register direct add s1, s2, s3 s1 s2
  s3
• Immediate addi s1, s2, 200 s1 s2 200
• Baseindex lw s1, 200(s2) s1 mem200
  s2
• PC-relative beq s1, s2, 200 if (s1 s2)
• PC PC42004
• Often, the type of addressing mode depends on the
  type of operation being performed (e.g. branches
  all use PC relative)
• A summary of MIPS addressing modes is given on
  the back cover of the book.

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MIPS Addressing Modes/Instruction Formats
All MIPS instructions are 32 bits wide - fixed
length
add s1, s2, s3
Register (direct)
op
rs
rt
rd
register
Immediate
addi s1, s2, 200
immed
op
rs
rt
Baseindex
immed
op
rs
rt
Memory
register
lw s1, 200(s2)
PC-relative
immed
op
rs
rt
Memory
PC
beq s1, s2, 200
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Class Summary

• Key components of an ISA are the instruction set
  and instruction format
• Today we covered for MIPS
• Three instruction types/formats (R-type, I-type,
  J-type)
• Basic math instructions (add, sub, addi)
• Data transfer instructions (lw, sw, lui)
• Control/branch (beq, bne, j)
• Equality test instructions (slt, slti)
• Next time we move onto procedures