CS 2200

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CS 2200

• Presentation 6d
• Introduction to Pipelining

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Questions?
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So far...

• We examined a simple design concept having a
  CPI of 1.
• Requirements
• Sufficient functional units to perform all
  necessary steps for every instruction
  simultaneously (e.g. 3 ALUs)
• Clock cycle long enough for most complex
  instruction to execute
• Requires separate memories for instructions and
  data

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And...

• We've looked at a typical multicycle design, the
  LC-2200
• Single memory for instructions and data
• One ALU
• One or more registers after each functional unit
• Multiplexors
• Bus design
• Do we need a bus based design?

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Question

• Do we need a bus?
• Yes
• No

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Functional Units Busy?

• During the course of execution of an instruction
  are the functional units all kept busy?
• How can we use most of the functional units in
  every clock cycle?

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Pipelining
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Need for Speed

• CPI of 1 was too slow
• Multicycle made things better
• But we want to go faster.
• Can we break our instruction into pieces?

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Passage of an Instruction

• IF Instruction Fetch
• ID Instruction Decode
• EX Execute (or calculate address)
• MEM Memory access (load or store)
• WB Write Back (from ALU or memory)

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An Example

• Assume processor spends
• 2 cycles to do IF, EX, MEM
• 1 cycle to do ID and WB
• Consider 3 successive load instructions
• how much time to execute?
• picture the execution
• how can you make this faster?

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24 Cycles
How can you make this faster?
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Laundry Break?
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Laundry

• We have the following
• A washer
• A dryer
• A person who irons/folds clothing
• A person who puts the clothing away
• Each of the above has a 30 minute cycle time
• Given a load of dirty laundry how long to do the
  complete job?
• Transfer time negligible.

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Base Case
2 hours
W
D
S
F
How long for 4 loads?
2 hours/load
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4 Load Case
8 hours
Can we do better?
2 hours/load
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4 Load Case
3.5 hours
W
D
S
F
W
D
S
F
W
D
S
F
W
D
S
F
Note Actual time to completely do one load
unchanged. Some time required to fill
pipeline. Steady state improvement depends on
number of units
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Question 4 Load Case

• How many hours/load?
• 0.5 hours/load
• 0.875 hours/load
• 2.0 hours/load

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12 Load Case
7.5 hours
.625 hours/load
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An Example

• Assume processor spends
• 2 cycles to do IF, EX, MEM
• 1 cycle to do ID and WB
• Consider 3 successive load instructions
• how much time to execute?
• picture the execution
• how can you make this faster?

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24 Cycles
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New Concept

• Can we try and separate the functional units into
  groupings or stages?
• Equivalent to saying the IF functional units
  will be like the washer.
• The ID units will be like the dryer and so
  on...
• May need to add back some functional units AND
  nix the bus!

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Step One
M X
1
P C
Instr Mem
DPRF
A
Data Mem
M X
M X
D
SE
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R-Type
M X
1
P C
Instr Mem
DPRF
A
Data Mem
M X
M X
D
SE
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LW
M X
1
P C
Instr Mem
DPRF
A
Data Mem
M X
M X
D
SE
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SW
M X
1
P C
Instr Mem
DPRF
A
Data Mem
M X
M X
D
SE
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BEQ
M X
1
P C
Instr Mem
DPRF
BEQ
A
Data Mem
M X
M X
D
SE
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Pipelining

• Clearly we have broken the design into stages but
  there is still a connection.
• Stage n is holding data/register numbers/etc.
  that stage n1 needs...
• Solution More registers to hold critical
  information

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PipeLined
M X
1
P C
Instr Mem
DPRF
BEQ
A
Data Mem
M X
M X
D
SE
WB
EX
MEM
ID
IF
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R-Type
M X
1
P C
Instr Mem
DPRF
BEQ
A
Data Mem
M X
M X
D
SE
WB
EX
MEM
ID
IF
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R-Type
M X
1
P C
Instr Mem
DPRF
BEQ
A
Data Mem
M X
M X
D
SE
WB
EX
MEM
ID
IF
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R-Type
M X
1
P C
Instr Mem
DPRF
BEQ
A
Data Mem
M X
M X
D
SE
WB
EX
MEM
ID
IF
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R-Type
M X
1
P C
Instr Mem
DPRF
BEQ
A
Data Mem
M X
M X
D
SE
WB
EX
MEM
ID
IF
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R-Type
M X
1
P C
Instr Mem
DPRF
BEQ
A
Data Mem
M X
M X
D
SE
WB
EX
MEM
ID
IF
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Question

• I understand this perfectly
• I sort of understand this
• I have mixed emotions and sometimes I feel like
  slappy myself silly
• I'm sort of lost
• So I put the oil in which end of the pipeline?

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R-Type
M X
1
P C
Instr Mem
DPRF
BEQ
A
Data Mem
M X
M X
D
SE
WB
EX
MEM
ID
IF
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13 cycles
WB
EX
ID
IF
MEM
WB
EX
ID
IF
MEM
WB
EX
ID
IF
MEM
Well, this is like a no-brainer!
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See any problems?
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The Dukes of Hazard

• Hazards
• Structural
• Control
• Data

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The Dukes of Hazard

• Hazards
• Structural
• Hardware cannot support desired instructions at
  the moment
• Dealing with Structural Hazards
• Replace bus with pipeline design
• Multiple memories

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The Dukes of Hazard

• Hazards
• Structural
• Hardware cannot support desired instructions at
  the moment
• Dealing with Structural Hazards
• Replace bus with pipeline design
• Multiple memories
• Control
• Need to make a decision but dont have results
  yet
• Stall

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WB
EX
ID
IF
MEM
add beq lw
WB
EX
ID
IF
MEM
WB
EX
ID
IF
MEM
Can be costly
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One solution...

• beq s0, s2, label
• add s1, s2, s3
• This instruction gets executed no matter what! So
  sometimes you will see
• beq s0, s2, label
• nop

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Another...Branch Prediction

• How accurately can branches be predicted?
• 30 of the time correctly
• 50
• 70
• 90

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The Dukes of Hazard

• Hazards
• Structural
• Hardware cannot support desired instructions at
  the moment
• Dealing with Structural Hazards
• Replace bus with pipeline design
• Multiple memories
• Control
• Need to make a decision but dont have results
  yet
• Stall (Can put instruction in slot!)
• Predict
• If correct, life is good
• If wrong, will need to squash some instructions
• Branch Target Buffer

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Precedence/Dependence

• a b c
• d e f
• g h i
• Could these three statements be executed in
  parallel?

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Precedence

• a d c
• d s g

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Dependence

• a b c
• d a g

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The Dukes of Hazard

• Hazards
• Data
• Need a result that isnt finished yet to make
  another calculation
• Forwarding or bypassing
• add t0, s1, s2
• add t3, t0, s4

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WB
EX
ID
IF
MEM
add add sub
WB
EX
ID
IF
MEM
WB
EX
ID
IF
MEM
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M X
1
P C
Instr Mem
DPRF
BEQ
A
Data Mem
M X
M X
D
SE
Forwarding Unit
WB
EX
MEM
ID
IF
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Questions
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