Memory Interfaces

1
Memory Interfaces
John DeHartApplied Research LaboratoryComputer
Science and Engineering Departmenthttp//www.arl.
wustl.edu/arl/projects/techX
2
Memory and Programming Interfaces

• Flash
• SDRAM
• JTAG
• ACE to CRM via JTAG for power up programming of
  CRM
• JTAG pings to ACE to ASP/Hs for verification
  purposes
• SelectMap
• for CRM programming of ASP/Hs
• CRM Access to
• Flash via OPB ACE Core and ACE chip
• JTAG via OPB ACE Core and ACE chip
• SelectMap via GPIO Core
• SDRAM
• Access for PPC Only
• IP Core for SDRAM interface available

3
Memory Interfaces
SDRAM
Control Processor
SDRAM CTRL Core
10/100 Core
ACE
OPB ACE Core
PPC Access to JTAG Flash
PPC
Flash
ITIF Core
GPIO
Low rate Ctrl Msgs
High Speed Interface
JTAG Tst
JTAG Pins
HW Switch
SelectMap
Out
In
CRM
JTAG Chain
ASP/H-1
ASP/H-2
4
Memory and Programming Interfaces

• Bitfiles coming in to CRM go into SDRAM via PPC
• Bitfiles going to SelectMap come from SDRAM via
  PPC
• PPC uses GPIO to access selectmap
• Control messages coming from High Speed interface
  go through ITIF core.
• PPC is only entity with an interface to SDRAM
• Does PPC control allocation of memory?
• When CP wants to deposit a bitfile in memory,
  does it know what address to put it at or does it
  have PPC allocate the memory and report back
  where it is?
• Seems like PPC has to control this.

5
Boot Scenario

• On PowerUp CRM is programmed from a default
  bitfile stored in the Flash
• There is no SPROM!
• File system on Flash is set up so there is a
  default bitfile for the CRM FPGA
• Programming of CRM happens via JTAG.
• Once CRM is up, as part of Initialization phase
• It programs the ASP/H-1 and ASP/H-2 with default
  bitfiles also stored in the Flash
• PPC reads bitfile(s) from Flash and writes them
  to SDRAM
• PPC reads bitfile(s) from SDRAM and writes to the
  GPIO interface connected to the SelectMap pins
• one set of pins for each FPGA to be programmed

6
ASP/H Plugin Programming Scenario

• PPC receives a control message to load a plugin
  in ASP/H-1
• If Plugin bitfile resides in Flash
• PPC reads bitfile from Flash and writes it to
  SDRAM
• PPC reads bitfile from SDRAM and writes to the
  GPIO interface connected to the SelectMap pins
• This is a partial re-programming
• Is there any massaging of bitfile that needs to
  happen to get it into the correct plugin slot?
• If so, is massaging done while it is in SDRAM?
• If Plugin already resides in SDRAM
• PPC reads bitfile from SDRAM and writes to the
  GPIO interface connected to the SelectMap pins
• This is a partial re-programming
• Is there any massaging of bitfile that needs to
  happen to get it into the correct plugin slot?

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Bitfile Programming Control Operations

• Control Operations
• Each operation may include multiple control
  messages
• Allocate memory
• Load memory
• Read memory
• Load Plugin
• etc.
• Fields may include
• Memory address
• Memory size
• Flash file system identifiers
• Plugin Slot ID
• ASP/H
• etc

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Bitfile Programming Control Operations

• Control Operations
• Load Incoming Bitfile into Memory
• coming in from 10/100 or RocketIO
• Read Bitfile from Memory
• going out to 10/100 or RocketIO
• Load Bitfile from Flash into Memory
• Write Bitfile to Flash from Memory
• Program ASP/H- with Bitfile in Memory
• Read Plugin Slot of ASP/H- into Memory
• NOTE
• All bitfile operations are TO or FROM Memory

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Bitfile Path (CP via 10/100 to SDRAM)
SDRAM
Control Processor
SDRAM CTRL Core
10/100 Core
ACE
OPB ACE Core
PPC Access to JTAG Flash
PPC
Flash
ITIF Core
GPIO
Low rate Ctrl Msgs
High Speed Interface
JTAG Tst
JTAG Pins
HW Switch
SelectMap
Out
In
CRM
ASP/H-1
JTAG Chain
ASP/H-2
10
Bitfile Path (CP via 10/100 to SDRAM)
SDRAM
Control Processor
SDRAM CTRL Core
10/100 Core
ACE
OPB ACE Core
PPC Access to JTAG Flash
PPC
Flash
ITIF Core
GPIO
Low rate Ctrl Msgs
High Speed Interface
JTAG Tst
JTAG Pins
HW Switch
SelectMap
Out
In
CRM
ASP/H-1
JTAG Chain
ASP/H-2
11
Bitfile Path (RocketIO to SDRAM)
SDRAM
Control Processor
SDRAM CTRL Core
10/100 Core
ACE
OPB ACE Core
PPC Access to JTAG Flash
PPC
Flash
ITIF Core
GPIO
Low rate Ctrl Msgs
High Speed Interface
JTAG Tst
JTAG Pins
HW Switch
SelectMap
Out
In
CRM
ASP/H-1
JTAG Chain
ASP/H-2
12
Bitfile Path (SDRAM to RocketIO)
SDRAM
Control Processor
SDRAM CTRL Core
10/100 Core
ACE
OPB ACE Core
PPC Access to JTAG Flash
PPC
Flash
ITIF Core
GPIO
Low rate Ctrl Msgs
High Speed Interface
JTAG Tst
JTAG Pins
HW Switch
SelectMap
Out
In
CRM
ASP/H-1
JTAG Chain
ASP/H-2
13
Bitfile Path (Flash to SDRAM)
SDRAM
Control Processor
SDRAM CTRL Core
10/100 Core
ACE
OPB ACE Core
PPC Access to JTAG Flash
PPC
Flash
ITIF Core
GPIO
Low rate Ctrl Msgs
High Speed Interface
JTAG Tst
JTAG Pins
HW Switch
SelectMap
Out
In
CRM
ASP/H-1
JTAG Chain
ASP/H-2
14
Bitfile Path (SDRAM to Flash)
SDRAM
Control Processor
SDRAM CTRL Core
10/100 Core
ACE
OPB ACE Core
PPC Access to JTAG Flash
PPC
Flash
ITIF Core
GPIO
Low rate Ctrl Msgs
High Speed Interface
JTAG Tst
JTAG Pins
HW Switch
SelectMap
Out
In
CRM
ASP/H-1
JTAG Chain
ASP/H-2
15
Bitfile Path (SDRAM to APS/H-1)
SDRAM
Control Processor
SDRAM CTRL Core
10/100 Core
ACE
OPB ACE Core
PPC Access to JTAG Flash
PPC
Flash
ITIF Core
GPIO
Low rate Ctrl Msgs
High Speed Interface
JTAG Tst
JTAG Pins
HW Switch
SelectMap
Out
In
CRM
ASP/H-1
JTAG Chain
ASP/H-2
16
Bitfile Path (APS/H-1 to SDRAM)
SDRAM
Control Processor
SDRAM CTRL Core
10/100 Core
ACE
OPB ACE Core
PPC Access to JTAG Flash
PPC
Flash
ITIF Core
GPIO
Low rate Ctrl Msgs
High Speed Interface
JTAG Tst
JTAG Pins
HW Switch
SelectMap
Out
In
CRM
ASP/H-1
JTAG Chain
ASP/H-2
17
Bitfile Path (SDRAM to ASP/H-2)
SDRAM
Control Processor
SDRAM CTRL Core
10/100 Core
ACE
OPB ACE Core
PPC Access to JTAG Flash
PPC
Flash
ITIF Core
GPIO
Low rate Ctrl Msgs
High Speed Interface
JTAG Tst
JTAG Pins
HW Switch
SelectMap
Out
In
CRM
ASP/H-1
JTAG Chain
ASP/H-2
18
Bitfile Path (ASP/H-2 to SDRAM)
SDRAM
Control Processor
SDRAM CTRL Core
10/100 Core
ACE
OPB ACE Core
PPC Access to JTAG Flash
PPC
Flash
ITIF Core
GPIO
Low rate Ctrl Msgs
High Speed Interface
JTAG Tst
JTAG Pins
HW Switch
SelectMap
Out
In
CRM
ASP/H-1
JTAG Chain
ASP/H-2