LECTURE 12 DIGITAL ELECTRONICS

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LECTURE 12 DIGITAL ELECTRONICS
Dr Richard ReillyDept. of Electronic
Electrical EngineeringRoom 153, Engineering
Building
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Comparison of Digital IC Families
All of the performance ratings are for a NAND
gate in each series.
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CMOS Circuits

• CMOS NAND Gate
• Note
• Ignoring initially the Aspect Ratios associated
  with each transistor

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CMOS Circuits

• Output pull-up to VDD provided by two P-Channel
  MOSFETs with their drain-to-source channels in
  parallel.
• Two N-channel MOSFETs with their drain-to-source
  channels in series provide the output pull-down
  to ground.

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CMOS Circuits

• The gate terminal of each PMOS is connected to
  the gate terminal of a separate N-Channel MOS
• thus forming the input to the CMOS NAND gate
  circuit.
•  
• NOTE
• Each input is accommodated by a separated CMOS
  complementary pair.
•  
•  
• The logical NAND output VNAND is taken at the
  node between the stacked NMOS pull-down devices
  and the parallel PMOS pull-up devices.

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CMOS Circuits

• For VA and VB low, two output pull-up paths to
  VDD are present through PA and PB
•   
• For VA and VB high, a single output pull-down
  path to ground through NA and NB is present

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Output High State

• Both Inputs Low
• ? VSG,P sufficient to bring both PMOS transistors
  into active mode of operation
• ? pull-up paths are provided by both PMOS
  devices.
•  
• ? VGS,N insufficient thus both NMOS transistors
  in cut-off.
• ? no pull-down path exists
•  
• Overall ? CMOS NAND gate is in the output high
  states for both inputs low.

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Output High Voltage ? VOH

• Sum of PMOS drain current is equal to drain
  current of NB ( and NA)
• With NB cut-off for both inputs low
• ?
• With each drain current zero
• the source-to-drain voltage of both P-Channel
  MOSFETs are
• ? VOH (CMOS NAND) VDD

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Output High State VA low, VB high

• With a single input low, output pull-up path to
  VDD exists through drain-to-source channel of
  corresponding P-Channel MOSFET (PA in this case)
•  
• If VA is low (ltVT,N)
• ? VGS,NA is insufficient to turn on NA.
• no conduction path exists to ground to source of
  NB
• regardless of VB, no output pull-down path to
  ground exists.
•  
• With VA low and VB high
• ? NAND gate in the output HIGH state

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Output High State VA high, VB low

• As with previous case, a single input low places
  the corresponding PMOS in active operation.
• ? providing a pull-up path to VDD (PB in this
  case).
•  
• With VA is high
• ? VGS,NA is sufficient to operate NA in active
  mode.
• Highly conductive path from ground to source of
  NB exists.
• ? with VB cut-off, no output pull-down path to
  ground exists.
•  
• With VA high and VB low
• ? NAND gate still in the output HIGH state

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Output High State VA high, VB low

• NOTE
• With NA active and NB cut-off
• drain current through NA and NB is
• ? active MOSFET with zero drain current has a
  drain-to-source voltage of 0V.
• Hence with NA active and NB cut-off
• ? source of NB is at a virtual ground.

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Output Low State

• Both inputs high
• If both inputs of the CMOS NAND are high, NA and
  NB are both active
• ? output pull-down path to ground through series
  drain-to-source channels of NA and NB.
•  
• With both inputs high ? source-to-gate voltages
  of both PA and PB are insufficient to bring them
  into active operation.
• ? no output pull-up path to VDD exists.
•  
• With both inputs high
• ? NAND gate is in the output LOW state.

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Output Low Voltage ? VOL

• Since the drain current of NA (and NB) is equal
  to the sum of the drain currents of PA and PB,
• ? with PA and PB cut-off, the drain currents of
  NA and NB are zero.
•  
• Since NA and NB are active with drain currents
  zero
• ? the drain-to-source voltages are also zero.
•  
• With
• ? VOL (CMOS NAND) 0

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Ordering of inputs

• If the NAND gate is intended to be used as an
  enabling-inverter.
• enable signal should be the input to the NMOS
  device at the bottom of the stack
• logical signal should be the input to the NMOS
  device at the top of the stack.
• Due to the dynamic switching characteristics of
  CMOS NAND gates.

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Ordering of inputs

• Enable signals will in general switch less often
  than logic signals

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Ordering of inputs

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Ordering of inputs

• With the bottom NMOS device active
• ? source of the top NMOS device is at virtual
  ground.
•  
• The switching speed of the NAND gate due to the
  logical input is then the switching speed of the
  simpler inverter.

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Ordering of inputs

• If enabling input used the top NMOS transistor
  and enable signal is high
• ? for output to switch due a change in the
  logical input, switching speed is dependent upon
  sum of the switching speeds of both N-Channel
  MOSFETs.
•  
•  
• Demonstrates that the input that switches least
  often should be connected to the CMOS pair that
  has the bottom of the stack N-channel MOSFET.

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Channel Aspect (Width/Length) Ratios

• Saw in last lecture that the aspect ratio of the
  PMOS device should be approximately 2.5 times the
  NMOS aspect ratio.
• Why?
• is needed to achieve a symmetric VTC for the CMOS
  inverter.
• Due to the relative mobilities of electrons and
  holes in the channels of N- and P-Channel Silicon
  MOSFETs.

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Channel Aspect (Width/Length) Ratios

• For a 2-input CMOS NAND gate, output pull-down
  path is through the drain-to-source channels of
  two NMOS devices in NMOS stack.
• What effect does this have ?
• ? output pull-down path is twice the physical
  length of that in the CMOS inverter.

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Channel Aspect (Width/Length) Ratios

• To accommodate for this in design, channel widths
  of the NMOS devices are chosen to be double those
  of the inverter.
• For a two input CMOS NAND gate, the PMOS aspect
  ratio is 1.25 times the NMOS ratio.
• for a two-input CMOS NAND

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Adding More Inputs

• More inputs can be added to the CMOS NAND
• Include an additional PMOS device in the parallel
  PMOS pull-up
• Include an additional NMOS in the NMOS series
  pull-down for each additional input.
•  
• Since the output high and low voltages are not
  degraded by additional inputs
• ? the number of inputs to a CMOS NAND is limited
  only by switching speed considerations.

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Adding More Inputs

• Each additional input requires further widening
  of the NMOS channels.
• for a k-input CMOS NAND gate
• PMOS aspect ratio is related to NMOS aspect ratio
  by

for a k-input CMOS NAND
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Adding More Inputs

• The factor k results from the increased widening
  of the NMOS transistor channel,
• Necessary because of the increased length of the
  output pull-down path to ground through multiple
  NMOS transistor channels.

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CMOS NOR Gate
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Aspect Ratio

• For a two-input NOR gate
• PMOS and NMOS channel widths should have a ratio
  
• two-input CMOS NOR
• and in general
• for a k-input CMOS NOR

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Disadvantages of CMOS NOR Gates over CMOS NAMD
Gates

• Examining the aspect ratios for the transistors
  in the CMOS NAND, the total area of the NMOS and
  PMOS channels is seen to be
• For the CMOS NOR gate, the total area of the NMOS
  and PMOS channels is seen to be

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Disadvantages of CMOS NOR Gates over CMOS NAMD
Gates

• Discounting area required for wiring of devices
• CMOS NOR gates require approximately 33 more
  silicon surface area than CMOS NAND gates in CMOS
  integrated circuits
•  
• ? Best practice to use CMOS NANDS over CMOS NOR
  gates whenever possible.

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Transmission Gate

• A special CMOS circuit that is not available in
  the other digital logic families is the
  Transmission Gate.
• Essentially an electronic switch, which is
  controlled by an input logic level
• Used for simplifying the construction of various
  digital components when fabricated in CMOS
  technology.

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Transmission Gate

• Basic transmission gate consists of one NMOS and
  one PMOS transistor connected in parallel.
• The NMOS substrate is connected to ground
• The PMOS substrate is connected to VDD

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Transmission Gate

• When the NMOS gate terminal VNEN VDD
• PMOS gate terminal, VPEN 0 V
• both transistors conduct and there is a closed
  path between X and Y.
•  
•  
• When the NMOS gate terminal, VNEN 0V
• PMOS gate terminal, VPEN VDD
• both transistors are in cut-off and there is an
  open circuit between X and Y

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Transmission Gate

• The IEEE symbol for the transmission gate
• or
• To turn the TG on set VPEN to 0 and VNEN to 1

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Transmission Gate

• Suppose that a 0 is applied to date terminal X
  for transmission to Y.
•  
• The transmission gate is quite symmetrical
• X and Y are completely interchangeable
•  
• The NMOS transistor has the correct gate voltage
  applied to turn on, with X serving as the source
  (more negative) terminal, whereas the PMOS
  transistor is cut-off.

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Transmission Gate

• When a 1 is applied to X
• NMOS turns off
• PMOS turns on
•  
• Thus provides necessary data transmission path
  for the Logic1 signal.

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Transmission Gate

• A transmission gate is a complete bi-directional
  switch
• One of its two transistors can always provide a
  data transmission path for a variable signal
  applied to either of its terminals.

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Transmission Gate

• Control input C is connected directly to the NMOS
  gate and its inverse to the PMOS gate terminal.
•  
•  
• When C1, switch closed, producing a path between
  X and Y.
• When C0, switch open, disconnecting X from Y.
•  
•  

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Exclusive OR-gate

• Various CMOS circuits can be formed by
  transmission gates.
• Exclusive OR Gate
• Formed from two transmission gates and two
  inverters.

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Exclusive OR-gate

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Exclusive OR-gate

• Input A controls paths in the transmission gates.
• Input B is connected to output Y, through the
  transmission gates.
•  
• When A 0
• TG1 is closed, Output Y Input B
•  
• When A 1
• TG2 is closed, Output Y complement of Input B

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Multiplexor

• CMOS 4-to-1 multiplexor can be implemented by
  CMOS transmission gates.

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Multiplexor

• Each box shows the condition for the transmission
  gate to be closed.
• ? If S0 0 and S1 0,
• ? closed path from input I0 to output Y
• though the two TGs marked with S0 0 and S1
  0.
•  
• three other inputs are disconnected from the
  output by one of the other TG circuits.

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Gated D Latch

• Level sensitive D flip-flop or Gated D latch can
  also be formed from transmission gates.
•  
• C input controls the two transmission gates

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Gated D Latch

• When C 1
• ? TG connected top input D has a closed path and
  the one connected to output Q has an open path.
•  
• This produces an equivalent circuit from input D
  through two inverters to output Q
•  
• Thus output follows the data input as long C
  remains active.

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Gated D Latch

• When C switches from 1 ? 0
• ? first TG disconnects input D from the circuit
  and the second TG produces a closed path between
  the two inverters at the output.
•  
• ? the value that was present at the input D at
  the time that C went from 1 ? 0 is retained at
  the Q output.

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Summary

• CMOS Circuits are very advantageous
• Advantages due to implementation

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