Lecture 3 Transistors, Wires,

1
Lecture 3 Transistors, Wires, Parasitics

• Pradondet Nilagupta
• pom_at_ku.ac.th
• Department of Computer Engineering
• Kasetsart University

2
Acknowledgement

• This lecture note has been summarized from
  lecture note on Introduction to VLSI Design, VLSI
  Circuit Design all over the world. I cant
  remember where those slide come from. However,
  Id like to thank all professors who create such
  a good work on those lecture notes. Without those
  lectures, this slide cant be finished.

3
Where we are...

• Last time
• CMOS Processing
• Today
• Transistor Modes of Operation
• More about Wires Vias
• Parasitics

4
Roadmap for the term major topics

• VLSI Overview
• CMOS Processing Fabrication
• Components Transistors, Wires, Parasitics
• Design Rules Layout
• Combinational Circuit Design Layout
• Sequential Circuit Design Layout
• Standard-Cell Design with CAD Tools Verilog
• Mixed Signal Concerns D/A, A/D Conversion
• Design Project Complete Chip

5
Review - Transistor Structure
6
N Transistor Operation - Cutoff

• Vgs ltlt Vt Transistor OFF
• Majority carrier in channel (holes)
• No current from source to drain

7
N Transistor Operation - Subthreshold

• 0 lt Vgs lt Vt Depletion region
• Electric field repels majority carriers (holes)
• Depletion region forms - no carriers in channel
• No current flows (except for leakage current)

8
N Transistor Operation - ON

• Vgs gt Vt , VDS0 Transistor ON
• Electric field attracts minority carriers
  (electrons)
• Inversion region forms in channel
• Depletion region insulates channel from substrate
• Current can now flow from drain to source!

9
N Transistor Operation - Linear

• Vgs gt Vt , VDS ltVGS -VT Linear (Active) mode
• Combined electric fields shift channel and
  depletion region
• Current flow dependent on VGS, VDS

10
N Transistor Operation - Saturation

• Vgs gt Vt , VDS gtVGS -VT Saturated mode
• Channel pinched off
• Current still flows due to electron drift
• Current flow dependent on VGS

11
P Transistor Operation

• Opposite of N-Transistor
• Vgs gtgt Vt Transistor OFF
• Majority carrier in channel (electrons)
• No current from source to drain
• 0 gt Vgs gt Vt Depletion region
• Electric field repels majority carriers
  (electrons)
• Depletion region forms - no carriers in channel
• No current flows (except for leakage current)
• Vgs lt Vt , VDS0 Transistor ON
• Electric field attracts minority carriers (holes)
• Inversion region forms in channel
• Depletion layer insulates channel from substrate
• Current can now flow from source to drain!

12
P Transistor Modes of Operation

• Vgs ltVt , VDS gtVGS -VT Linear (Active) mode
• Combined electric fields shift channel and
  depletion region
• Current flow dependent on VGS, VDS
• Vgs lt Vt , VDS ltVGS -VT Saturation mode
• Channel pinched off
• Current still flows due to hole drift
• Current flow dependent on VGS

13
N-type Transistor structure

• n-type transistor

14
0.25 micron transistor (Bell Labs)
gate oxide
silicide
source/drain
poly
15
Transistor layout

• n-type (tubs may vary)

L
w
16
I-V Characteristics of MOS Transistors
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Ideal Transistor Equations

• Cutoff Region Vgs lt Vt
• Linear Region Vds lt Vgs - Vt
• (EQ 2-1)
• Saturated Region Vds Vgs - Vt
• (EQ 2-2)
• (EQ 2-16)

18
More about Transistor Equations

• More about k'
• µ - effective surface mobility of carrier
• e - permittivity of gate insulator
• tox - thickness of gate insulator
• Beta - a measure of gain
• Important things to remember
• these equations are approximations
• Use circuit simulator (e.g. PSpice)for more
  accurate modeling

19
0.5 ?m transconductances

• From a MOSIS process
• n-type
• kn 73 ?A/V2
• Vtn 0.7 V
• p-type
• kp 21 ?A/V2
• Vtp -0.8 V

20
Current through a transistor

• Use 0.5 ?m parameters. Let W/L 3/2. Measure at
  boundary between linear and saturation regions.
• Vgs 2V
• Id 0.5k(W/L)(Vgs-Vt)2 93 ?A
• Vgs 5V
• Id 1 mA

21
MOSFET gate as capacitor

• Basic structure of gate is parallel-plate
  capacitor

gate

tox
SiO2
Vg
-
substrate
22
Parallel plate capacitance

• Formula for parallel plate capacitance
• Cox ?ox / tox
• Permittivity of silicon
• ?ox 3.46 x 10-13 F/cm2
• Gate capacitance helps determine charge in
  channel which forms inversion region.

23
Threshold voltage

• Components of threshold voltage Vt
• Vfb flatband voltage depends on difference in
  work function between gate and substrate and on
  fixed surface charge.
• ?s surface potential (about 2?f).
• Voltage on paralell plate capacitor.
• Additional ion implantation.

24
Body effect

• Reorganize threshold voltage equation
• Vt Vt0 ?Vt
• Threshold voltage is a function of
  source/substrate voltage Vsb.
• Body effect ? is the coefficienct for the Vsb
  dependence factor.

25
Example threshold voltage of a transistor

• Vt0 Vfb ?s Qb/Cox VII
• -0.91 V 0.58 V (1.4E-8/1.73E-7) 0.92
  V
• 0.68 V
• Body effect ?n sqrt(2q?SiNA/Cox) 0.1
• DVt ?nsqrt(?s Vsb) - sqrt(?s)
• 0.16 V

26
Channel length modulation length parameter

• ? describes small dependence of drain corrent on
  Vds in saturation.
• Factor is measured empirically.
• New drain current equation
• Id 0.5k (W/L)(Vgs - Vt) 2(l - l Vds)
• Equation has a discontinuity between linear and
  saturation regions---small enough to be ignored.

27
Gate voltage and the channel
gate
drain
source
current
Vds lt Vgs - Vt
Id
gate
drain
source
current
Vds Vgs - Vt
Id
gate
drain
source
Vds gt Vgs - Vt
Id
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Leakage and subthreshold current

• A variety of leakage currents draw current away
  from the main logic path.
• The subthreshold current is one particularly
  important type of leakage current.

29
Types of leakage current.

• Weak inversion current (a.k.a. subthreshold
  current).
• Reverse-biased pn junctions.
• Drain-induced barrier lowering.
• Gate-induced drain leakage
• Punchthrough currents.
• Gate oxide tunneling.
• Hot carriers.

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Subthreshold current

• Subthreshold current
• Isub ke(Vgs - Vt)/(S/ln 10)1-e-qVds/kT
• Subthreshold slope S characterizes weak inversion
  current.
• Subthreshold current is a function of Vt.
• Can adjust Vt by changing the substrate bias to
  control leakage.

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The modern MOSFET

• Features of deep submicron MOSFETs
• epitaxial layer for heavily-doped channel
• reduced area source/drain contacts for lower
  capacitance
• lightly-doped drains to reduce hot electron
  effects
• silicided poly, diffusion to reduce resistance.

32
Circuit simulation

• Circuit simulators like Spice numerically solve
  device models and Kirchoffs laws to determine
  time-domain circuit behavior.
• Numerical solution allows more sophisticated
  models, non-functional (table-driven) models, etc.

33
Spice MOSFET models

• Level 1 basic transistor equations of Section
  2.2 not very accurate.
• Level 2 more accurate model (effective channel
  length, etc.).
• Level 3 empirical model.
• Level 4 (BSIM) efficient empirical model.
• New models level 28 (BSIM2), level 47 (BSIM3).

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Some (by no means all) Spice model parameters

• L, W transistor length width.
• KP transconductance.
• GAMMA body bias factor.
• AS, AD source/drain areas.
• CJSW zero-bias sidewall capacitance.
• CGBO zero-bias gate/bulk overlap capacitance.

35
Threshold Voltage

• Depends on gate capacitance, physical constants
• When Vsb0
• (EQN 2-4)
• (EQN 2-5)
• (EQN 2-6)
• (EQN 2-7)
• (EQN 2-9)
• (EQN 2-10)

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Threshold Voltage - Body Effect

• Vt increases when Vsb gt0
• (EQN 2-11)
• (EQN 2-12)

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Subthreshold Current

• Current can flow even when transistor is off
• (EQ 2-17)

S - subthreshold slope (measured in mV/decade) q
- charge of an electron k - Boltzmanns
constant T - temperature (Kelvin)
38
Wires and Vias

• Creating wires (review)
• Deposit insulator on chip (SiO2)
• Deposit conducting material on chip
• Selectively remove using photolithography
• Use multiple layers so wires can cross over each
  other
• Vias (Contacts) - Connect between layers
• cuts etched through insulator
• Metal connects between layers (with significant
  resistance)

39
Wires and vias
metal 3
metal 2
vias
metal 1
poly
poly
p-tub
n
n
40
Metal migration (1/2)

• Current-carrying capacity of metal wire depends
  on cross-section. Height is fixed, so width
  determines current limit.
• Metal migration when current is too high,
  electron flow pushes around metal grains. Higher
  resistance increases metal migration, leading to
  destruction of wire.

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Metal Migration (2/2)

• High current density can cause metal molecules to
  move
• Solution size wires to keep current density with
  recommended range (book 1.5mA / µm width)
• Also a problem in vias

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Metal migration problems and solutions

• Marginal wires will fail after a small operating
  periodinfant mortality.
• Normal wires must be sized to accomodate maximum
  current flow
• Imax 1.5 mA/?m of metal width.
• Mainly applies to VDD/VSS lines.

43
Wiring Examples - Intel Processes
44
Diffusion wire capacitance

• Capacitances formed by p-n junctions

sidewall capacitances
depletion region
n (ND)
bottomwall capacitance
substrate (NA)
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Depletion region capacitance

• Zero-bias depletion capacitance
• Cj0 ?si/xd.
• Depletion region width
• xd0 sqrt(1/NA 1/ND)2?siVbi/q.
• Junction capacitance is function of voltage
  across junction
• Cj(Vr) Cj0/sqrt(1 Vr/Vbi)

46
Poly/metal wire capacitance

• Two components
• parallel plate
• fringe.

fringe
plate
47
Metal coupling capacitances

• Can couple to adjacent wires on same layer, wires
  on above/below layers

metal 2
metal 1
metal 1
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Example parasitic capacitance measurement

• n-diffusion bottomwall2 fF, sidewall2 fF.
• metal plate0.15 fF,
  fringe0.72 fF.

1.5 ?m
3 ?m
0.75 ?m
2.5 ?m
1 ?m
49
Parastic Elements

• So far, weve concentrated on getting circuit
  elements that we want for digital design
• Transistors
• Wires
• Parasitics - occur whether we want them or not
• Capacitors
• Resistors
• Transistors (bipolar and FET)

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Basic transistor parasitics (1/2)

• Gate to substrate, also gate to source/drain.
• Source/drain capacitance, resistance.

51
Basic transistor parasitics (2/2)

• Gate capacitance Cg. Determined by active area.
• Source/drain overlap capacitances Cgs, Cgd.
  Determined by source/gate and drain/gate
  overlaps. Independent of transistor L.
• Cgs Col W
• Gate/bulk overlap capacitance.

52
Capacitance (1/2)

• Transistors
• Depends on area of transistor gate
• Depends on physical materials, thickness of
  insulator
• Given for a specific process as Cg
• Diffusion to substrate
• Sidewall capacitance - capacitance from periphery
• bottomwall capacitance - capacitance to
  substrate
• See Eqns. 2-19 thru 2-22
• Given for a specific process as Cdiff,bot,
  Cdiff,side

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Capacitance (2/2)

• Metal to substrate
• Parallel plate capacitance is dominant
• Need to account for fringing, too
• Poly to substrate
• Parallel plate plus fringing, like metal
• Gotcha dont confuse poly over substrate with
  gate capacitance
• Sample parasitic values Table 2-4, p. 85
• Also important capacitance between conductors
• Metal1-Metal1
• Metal1-Metal2

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Resistance

• Depends on resistivity of material r (Rho)
• Sheet resistance Rs r /t see Table 2-4, p. 80
• Resistance R Rs L / W
• Corner approximation - count a corner as half a
  square

ExampleR Rs(poly) 13 2(1/2) 3(1/2)
squaresR 4?/sq 15.5 squares 62?
Corner (1/2 Square)
1/2 Square
1/2 Square
Corner (1/2 Square)
Corner (1/2 Square)
55
Wire resistance

• Resistance of any size square is constant

56
Mean-time-to-failure

• MTF for metal wires time required for 50 of
  wires to fail.
• Depends on current density
• proportional to j-n e Q/kT
• j is current density
• n is constant between 1 and 3
• Q is diffusion activation energy

57
Skin effect

• At low frequencies, most of copper conductors
  cross section carries current.
• As frequency increases, current moves to skin of
  conductor.
• Back EMF induces counter-current in body of
  conductor.
• Skin effect most important at gigahertz
  frequencies.

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Skin effect, contd

• Isolated conductor

• Conductor and ground

Low frequency
Low frequency
High frequency
High frequency
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Skin depth

• Skin depth is depth at which conductors current
  is reduced to 1/3 37 of surface value
• d 1/sqrt(p f m s)
• f signal frequency
• m magnetic permeability
• s wire conducitvity

60
Effect on resistance

• Low frequency resistance of wire
• Rdc 1/ s wt
• High frequency resistance with skin effect
• Rhf 1/2 s d (w t)
• Resistance per unit length
• Rac sqrt(Rdc 2 k Rhf 2)
• Typically k 1.2.

61
Transistor gate parasitics

• Gate-source/drain overlap capacitance

gate
source
drain
overlap
62
Transistor source/drain parasitics

• Source/drain have significant capacitance,
  resistance.
• Measured same way as for wires.
• Source/drain R, C may be included in Spice model
  rather than as separate parasitics.

63
Some Example Process Data

• Book Table 2-4, p. 80 - 0.5µm process
• AMI 1.5µm process (from www.mosis.org)
• TSMC 0. 5µm process (from www.mosis.org)

64
Parasitics - Final Notes

• These are approximate calculations
• Grossly oversimplified
• Advanced CAD tools (e.g. field solver) needed for
  accuracy
• Process Variation
• Parameter values are are not exact, but vary
  depending on manufacturing, etc.
• Typical process specifies a range for each
  parameter
• Must design chips to work for worst case -
  process corners

65
Example Problems - Parasitic Calculation (1/10)
30l
metal1
1l0.25µm
poly
ndiff
Rmetal1? Cmetal1?
Rpoly? Cpoly?
Rndiff? Cndiff?
Note see Table 2-4, p. 80 for parameters
66
Example Problems - Parasitic Calculation (2/10)
30l
metal1
1l0.25µm
poly
ndiff
Rmetal1 30l / 3l) 0.08?/o 0.8? Cmetal1
(30l 0.25µm/l) (3l 0.25µm/l) 0.04fF/µm2
(30l 3l 30l 3l) 0.25µm/l
0.09fF/µm 0.225fF 1.485fF 1.71fF
Note see Table 2-4, p. 80 for parameters
67
Example Problems - Parasitic Calculation (3/10)
30l
metal1
1l0.25µm
poly
ndiff
Rndiff (11l / 3l) 2?/o 7.33? Cndiff
(11l 0.25µm/l) (3l 0.25µm/l) 0.6fF/µm2
(11l 3l 11l 3l) 0.25µm/l
0.2fF/µm 1.24fF 1.4fF 2.64fF
Note see Table 2-4, p. 80 for parameters
68
Example Problems - Parasitic Calculation (4/10)
30l
metal1
1l0.25µm
poly
ndiff
Rpoly ((3l / 2l) 1/2o (8l / 2l)) 4?/o
24? Cpoly ( ((3l 0.25µm/l) (2l
0.25µm/l)) ((10l 0.25µm/l) (2l
0.25µm/l))) 0.09fF/µm2 (5l 10l 2l
8l 3l 2l) 0.25µm/l 0.04fF/µm 0.15fF
0.3fF 0.45fF
Note see Table 2-4, p. 80 for parameters
69
Example Problems - Parasitic Calculation (5/10)
30l
metal1
1l0.25µm
poly
ndiff
Rmetal10.8? Cmetal1 1.71fF
Rndiff7.33? Cndiff 2.64fF
Rpoly24? Cpoly 0.45fF
70
Example Problems - Parasitic Calculation (6/10)
1l0.25µm
A
What are the parasitic capacitances visible from
point A?
71
Example Problems - Parasitic Calculation (7/10)
1l0.25µm
A
What are the parasitic capacitances visible from
point A?
Cpoly (6l 0.25µm/l) (2l 0.25µm/l)
0.09fF/µm2 (6l 2l 6l 2l) 0.25µm/l
0.04fF/µm 0.675fF 0.16fF 0.84fF
72
Example Problems - Parasitic Calculation (8/10)
1l0.25µm
A
What are the parasitic capacitances visible from
point A?
Cgate (3l 0.25µm/l) (2l 0.25µm/l)
0.9fF/µm2 0.34fF Remember use Cg, not Cpoly
for transistor gates!
73
Example Problems - Parasitic Calculation (9/10)
1l0.25µm
A
What are the parasitic capacitances visible from
point A?
Coverhang (2l 0.25µm/l) (2l 0.25µm/l)
0.09fF/µm2 (2l 2l 2l 2l) 0.25µm/l
0.04fF/µm 0.0225fF 0.08fF 0.1fF
74
Example Problems - Parasitic Calculation (10/10)
1l0.25µm
A
What are the parasitic capacitances visible from
point A?
75
Latch-up

• CMOS ICs have parastic silicon-controlled
  rectifiers (SCRs).
• When powered up, SCRs can turn on, creating
  low-resistance path from power to ground. Current
  can destroy chip.
• Early CMOS problem. Can be solved with proper
  circuit/layout structures.

76
Parasitic SCR
circuit
I-V behavior
77
Parasitic Transistors

• Parasitic bipolar transistors form at N/P
  junctions
• Latchup - when parasitic transistors turn on
• Preventing latchup
• Add substrate contacts (tub ties) to reduce Rs,
  Rw (more about this later) OR
• Use Silicon-on-Insulator

78
Controlling Latchup - Substrate Contacts

• Purpose connect well/substrate to power supply
• Alternative term tub tie (used by book)
• Recommendations (source Weste Eshraghian)
• Conservative 1 substrate contact for every
  supply connection
• Less conservative 1 substrate contact for every
  5-10 transistors
• High-current circuits use guard rings

Substrate Contact
Substrate Contact
79
Solution to latch-up

• Use tub ties to connect tub to power rail. Use
  enough to create low-voltage connection.

80
Tub tie layout
p
metal (VDD)
p-tub
81
Coming Up

• Layout Design
• Design Rules
• Metal Migration