Combinational Logic and Design

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Combinational Logic and Design

• Anselmo Lastra

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Administration

• How did the lab go?

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Topics

• More logic primitives
• NAND, NOR, Exclusive-OR
• Combinational Design (Ch. 3)
• Real Devices
• Logic Families, Actual ICs, Gate delays
• Propagation delay

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NAND Gates

• NAND is NOT AND
• Very common

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NOR

• NOT OR
• Also common

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NAND is Universal

• Can express any Boolean Function
• Equivalents below

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Using NAND as Invert-OR

• Also reverse inverter diagram for clarity

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Sum of Products with NAND

• Easy to think of bubbles as canceling

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AND-OR Circuit Easy to Convert
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NOR Also Universal

• Dual of NAND

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Buffer

• No inversion
• No change, except in power or voltage
• Used to enable driving more inputs

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Exclusive OR

• Exclusive OR
• What lay people mean by or
• Symbol is ?
• Plus in a circle

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Parity Function

• Recall how parity works
• Ask class
• Write truth table for two input even parity
• What needs to be generated for parity bit?
• What function of two inputs gives you this?

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XOR Gives Odd Function

• As many inputs as necessary
• How do you get odd parity?
• Design even parity generator for 3-bit signal
• Perhaps make truth table and K-Map
• Draw with XOR, then sum-of-products w/ NAND gates
• How do you design a detector?
• How about a 7-bit ASCII character?

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Others
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Tri-State

• Output w/ 3 states H, L, and Hi-Z
• High impedance
• Behaves like no output connection if in Hi-Z
  state
• Allows connecting multiple outputs

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Multiplexed with Hi-Z

• Normal operation is blue area

Smoke
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CMOS Transmission Gates

• Act like electronic switches

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XOR w/ Transmission Gate
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Combinational Logic Design

• Ch. 3 takes us to hierarchical design
• Like youd use for a program of size
• Next time well move to Verilog
• Next lab will be in Verilog
• Then basic building blocks
• Adders, multiplexers, etc.

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Design Hierarchy

• Just like with large program, to design a large
  chip need hierarchy
• Divide and Conquer
• To create and also to understand
• Block is equivalent to object

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Example

• 9-input odd func (parity for byte)
• Check for even parity
• Block for schematic is box with labels

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Design Broken Into Modules

• Use 3-input odd functions

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Each Module uses XOR
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Use NAND to Implement XOR

• In case theres no XOR, for example

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Design Hierarchy
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Components in Design

• RHS shows what must be designed

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Hierarchical Design

• No need to ever draw full schematic with every
  gate
• Abstract at the appropriate level

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Reuse is Common

• Certainly forced because of availability of parts
  (chips)
• Also the design cycle was very long
• Now more flexibility with programmable logic
• Youll see many logic blocks available in Xilinx
  library

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Top Down Design

• Ideally you specify top level of design and work
  your way down
• Real life isnt that way
• Usually
• Work some at top
• Build/test some low-level blocks
• Go back to top level
• Just like real programs
• Big projects (like Pentium) done with
  architecture and levels of simulators

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Computer-Aided Design (CAD)

• Circuits of todays complexity rely on design
  tools
• Libraries of designs
• Can be purchased
• Some free
• Complexity varies gates to microprocessors
• www.opencores.org
• Software logic simulator crucial

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Design Entry

• Schematic capture
• What you did in lab
• Hardware Description Language (HDL)
• VHDL
• Verilog
• Abel
• Higher level possible C-like and Java-like

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Flow of CAD System
Replaces Generic Gates with ones available in
Technology Library
Generic Gates

• Netlist is description of connections

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Implementation Technologies

• Overview of available (and older)
• Well come back to this several times
• At different levels

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Integrated Circuit

• Known as IC or chip
• Silicon containing circuit
• Later in semester well examine in more detail
• Packaged in ceramic or plastic
• From 4-6 pins to hundreds
• Pins wired to pads on chip

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Bonding
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Levels of Integration

• SSI
• Individual gates
• MSI
• Things like counters, single-block adders, etc.
• Like stuff well be doing next
• LSI
• VLSI
• Larger circuits, like the FPGA, Pentium, etc.

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Logic Families

• RTL, DTL earliest
• TTL was used 70s, 80s
• Still available and used occasionally
• 7400 series logic, refined over generations
• CMOS
• Was low speed, low noise
• Now fast and is most common
• BiCMOS and GaAs
• Speed

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Catalogs

• Catalog pages describe chips
• Look at
• http//focus.ti.com/lit/ds/scas014c/scas014c.pdf
• Specifications
• Pinouts
• Packages
• Electrical characteristics

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Electrical Characteristics

• Fan in max number of inputs to a gate
• Fan out how many standard loads it can drive
  (fan in usually 1)
• Voltage often 3.3v or 5v
• Noise margin how much electrical noise can
  tolerate
• Power dissipation how much power chip needs
• TTL high
• Some CMOS low (but look at heat sink on a
  Pentium)
• Propagation delay next

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Propagation Delay

• Max of high-to-low and low-to-high
• Maximum and typical given

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Simulation Delays

• A simulator can model timing phenomena in two
  ways
• Transport delay
• Output after a specified time
• Inertial delay
• No effect if input occurs for time that is too
  short (cant overcome inertia) smaller than
  transport delay time

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Effect of Transport Delay (blue)

• Delay just shifts signal in time

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Effect of Inertial Delay

• Blue Propagation delay time Black
  Rejection time

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Fan Out and Delay

• Practical fan out of CMOS limited by capacitance
  of input gates
• More gates drive, longer time for signal to
  change
• So delay time for CMOS affected by fan out
• Wire delay very important

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Example using ISE

• Look at Lab 1
• Synthesis report timing prediction
• Text-based Post Place Route timing report
• View routed design
• To see where components and I/O buffers are
  located

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Cost

• Can be number of chips with older technology
• Area for VLSI design
• Number of LUTs on FPGA

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Today

• Other gate types
• NAND, NOR, XOR
• Design paradigm
• Talked about real devices
• Propagation delays
• First look at how fast your circuits could work

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Next Time

• Design example
• Coding in Verilog
• Verification

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Read

• Chapter 3
• Sections 3, 5, 6
• Scan Section 4
• Well just cover nomenclature and technology, not
  the design