COMP541 Sequencing and Control

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COMP541Sequencing and Control

• Montek Singh
• Mar 29, 2007

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Topics

• Starting on Chapter 8
• Control unit
• Multiplier as example
• Today hardwired control
• Next time microprogrammed control

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Control Units

• Two types
• Programmable
• Non-programmable (what you are implementing)
• Look at non-programmable first
• A multiplier

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Algorithmic State Machines

• Like a flowchart to express hardware algorithms
• ASM describes sequence of events and timing
  relationships
• Can then turn automatically into circuit

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Components (3 of them)

• State box specifies a state
• And what register ops and/or outputs happen when
  in this state

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Decision Box

• Based on a single variable
• Paths for 0 and 1

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Conditional Output

• Register operation is executed if box is reached
  after decision

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Example

• Somewhat like start of CPU

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ASM Block

• Another example
• Machine idle until START
• Then A set to 0
• Decision based on Q0

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Timing is Normal

• States change at clock (this is posedge clocked)

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Example Binary Multiplier

• Two versions
• Hardwired control
• Microprogrammed
• Multiplies two unsigned binary numbers

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Multiplication Algorithm

• Either select multiplicand or zero
• Shift left one each time
• Sum all to get product
• Result size 2n

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Hardware-Friendly Variation

• Partial product
• Right shift
• Only n bit adder instead of 2n
• Each step either add/shift or just shift

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Datapath
Counter size ceiling of log n
Holds multiplier as well as shifted result. How?
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More
Counter preset to n-1. Counts down.
Signals when it hits zero.
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ASM Chart

• Look at it in parts

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Idle

• Wait until G asserted
• Then clear C and A, and set P to n-1
• Then multiplication begins

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Multiplication

• Test Q0
• If 1, add B
• Recall that MUL1 done all at same time
• What happens to C?
• Test counter zero

To IDLE
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Hardwired Control

• Two aspects to control
• Control of the microoperations
• Generating signals, such as those for the ALU
  operations, register numbers, etc.
• Sequencing
• What happens next?
• The order of any microoperations
• Like states of our locks

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Create Control Sig from ASM

• Can look at it one set at a time

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Register A

• All microops on Reg A
• Last column is combinational expression that
  controls microop
• Signal name is just assigned by designer

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Register B

• LOADB is not listed on ASM chart
• Its an external signal that commands reg to load

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Flip-Flop C
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Register Q

• Similar
• External load
• Shift same as for Reg A

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Counter P

• Both of counters Ops happen with others, so no
  new signals

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Sequencing

• Now can look purely at sequencing
• Only decisions affecting next state are left
• Q0 did not affect state

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Have State Diagram

• This should look familiar
• Similar to state diagram, such as used in your
  locks
• Well look at manual design briefly, then Verilog

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What We Need to Do

• Have decided how to generate control signals
• Have separated control of timing
• Now implement in logic

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Sequence Register and Decoder

• Make register with enough bits to represent
  states
• Add decoder to generate signal for each state
• For our example (3 states) need
• 2-bit register
• 2-to-4 decoder (only need 3 lines of it)

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State Table

• Lets recall how this works by stepping through

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Generate Signals Using Tables
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Circuit
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One-Hot Encoding (review)

• One Flip-Flop per state
• Only one of the FFs has value 1
• The single 1 propagates, controlled by
  combinational logic
• Seems wasteful at first glance
• Need n FFs instead of log n
• However, its easy to design

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Design from ASM

• Just use transformation rules to convert ASM to
  logic
• Heres state box

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Decision Box

• Represents both possibilities

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Junction

• Junction just an OR gate

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Conditional Output

• The action is triggered by the generated control
  line

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Circuit from Chart

• FFs labeled 1, decisions 2, junctions 3, control 4

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Verilog Version

• Similar to the digital lock
• Case statement for sequence of states
• Transition to next state if criteria are true

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Verilog (1)

• module binary_multiplier_v (CLK, RESET, G, LOADB,
  LOADQ,
• MULT_IN, MULT_OUT)
• input CLK, RESET, G, LOADB, LOADQ
• input 30 MULT_IN
• output 70 MULT_OUT
• reg 10 state, next_state, P
• parameter IDLE 2'b00, MUL0 2'b01, MUL1
  2'b10
• reg 30 A, B, Q
• reg C
• wire Z
• assign Z P
• assign MULT_OUT A,Q

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Verilog (2)

• Reset or go to next state
• //state register
• always_at_(posedge CLK or posedge RESET)
• begin
• if (RESET 1)
• state lt IDLE
• else
• state lt next_state
• end

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Verilog (3) Next State

• //next state function
• always_at_(G or Z or state)
• begin
• case (state)
• IDLE
• if (G 1)
• next_state lt MUL0
• else
• next_state lt IDLE
• MUL0
• next_state lt MUL1
• MUL1
• if (Z 1)
• next_state lt IDLE
• else
• next_state lt MUL0
• endcase
• end

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Verilog (4) Datapath

• always_at_(posedge CLK)
• begin
• if (LOADB 1)
• B lt MULT_IN
• if (LOADQ 1)
• Q lt MULT_IN
• case (state)
• IDLE
• if (G 1)
• begin
• C lt 0
• A lt 4'b0000
• P lt 2'b11
• end
• MUL0
• if (Q0 1)
• C, A lt A B
• MUL1
• begin

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Simulation

• Multiply 1011 by 0110

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My version has no next_state

• //state register
• always_at_(posedge CLK or posedge RESET)
• begin
• if (RESET 1)
• state lt IDLE
• else
• case (state)
• IDLE
• if (G 1)
• state lt MUL0
• else
• state lt IDLE
• MUL0
• state lt MUL1
• MUL1
• if (Z 1)
• state lt IDLE
• else
• state lt MUL0

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Today

• Weve taken example
• Created ASM
• Divided into control and sequencing
• Looked at two ways to implement using logic
• Looked at Verilog example
• Next time
• Look at microprogrammed control of multiplier