CMOS VLSI DESIGN

1
CMOS VLSI DESIGN

• Kasin Vichienchom
• kvkasin_at_kmitl.ac.th
• Lecture3

2
CMOS Inverter Sizing

• According to switching voltage
• prefer to have VSW VDD/2
• According to propagation delay
• Prefer to have tPHL tPLH

3
Logic Circuits
Combinational
Sequential
Output
(
)
Output
(
)
f
In
f
In, Previous In
Ex Logic gates, mux, decoder, adder
Ex Registers, counters, oscillators memory
Source Jan Rabaey
4
Logic Styles

• Static CMOS circuits
• extension of the static CMOS inverter to multiple
  inputs
• output is connected to either VDD or GND via
  low-resistance path
• robustness, good performance, low power
  consumption
• Dynamic CMOS circuits
• rely on temporary storage of signal values on the
  capacitance of high-impedance circuits node
• less complex and operate faster
• prone to fail due to increased sensitivity to
  noise

5
Review Basic Logic Gates
Source Hodges
6
Review Basic Logic Gates
Source Hodges
7
Review Basic Logic Gates

• Tristate buffer produces Z when not enabled

Source Jan Rabaey
8
Review Basic Logic Circuits

• 21 multiplexer chooses between two inputs

Source Jan Rabaey
9
DeMorgans Laws
Source Hodges
10
Static Complementary MOS Circuits

• Structure of CMOS
• CMOS Gates and Layout
• Delay
• Power Dissipation

Source Jan Rabaey
11
Static Complementary MOS Circuits

• Structure of CMOS

Pull-Up Network (PUN) and Pull-Down Network (PDN)
are dual logic networks consisting of MOS
transistors in series/parallel connection
Source Jan Rabaey
12
CMOS Circuits N-Switche

• NMOS Transistors in Series/Parallel Connection

• Transistors can be thought as a switch controlled
  by its gate signal
• NMOS switch closes when switch control input is
  high

Y X if A and B
Y X if A or B
Source Jan Rabaey
13
CMOS Circuits

• PMOS Transistors in Series/Parallel Connection

• PMOS switch closes when switch control input is
  low

A
B
Y
X
A
B
Y
X
Source Jan Rabaey
14
CMOS Circuits Threshold Drop

• Why use PMOS for PUN and NMOS for PDN

VDD
VDD
PUN
D
S
VDD
D
S
0 ? VDD - VTn
0 ? VDD
VGS
VDD ? 0
VDD ? VTp
PDN
VGS
S
D
VDD
S
D
PMOS can pass VDD without VT drop Good for pass
logic 1 or H NMOS can pass GND without VT
drop Good for pass logic 0 or L
Source Jan Rabaey
15
CMOS Circuits
Source Jan Rabaey
16
Example 2-input NAND
Source Jan Rabaey
17
Example 2-input NOR
Source Jan Rabaey
18
Complex CMOS Gate
B
C
OUT D A (B C)
A
D
B
C
Source Jan Rabaey
19
Example XOR
Source Hodges
20
Example XNOR
Source Hodges
21
Example 21 Mux
Source Hodges
22
Static CMOS Properties

• Full rail-to-rail swing high noise margins
• Number of Transistor 2n where n is the number
  of input
• Logic levels not dependent upon the relative
  device sizes ratioless
• Always a path to Vdd or Gnd in steady state low
  output impedance
• Extremely high input resistance nearly zero
  steady-state input current
• No direct path steady state between power and
  ground no static power dissipation
• Propagation delay function of load capacitance
  and resistance of transistors

Source Jan Rabaey
23
Layout Methodology

• Cell Design

• Standard Cells
• General purpose logic
• Can be synthesized
• Same height, varying width
• Datapath Cells
• For regular, structured designs (arithmetic)
• Includes some wiring in the cell
• Fixed height and width

Source Jan Rabaey
24
Layout Methodology

• Standard Cell very popular due to high degree
  of automation

Routing channel
VDD
P-diff
M1
signals
M2
Poly
N-diff
GND
Routing channel
Source Jan Rabaey
25
Layout Methodology

• Standard Cell Layout

Routing channel requirements are reduced by
presence of more interconnect layers
Source Jan Rabaey
26
Layout Styles

• Standard Cell Layout 1990s

Mirrored Cell
VDD
No Routing channels
VDD
P-diff
M1
N-diff
M2
M3
GND
GND
Mirrored Cell
Source Jan Rabaey
27
Layout Styles

• Standard Cells

N Well
Fixed Cell Height
Out
In
Cell boundary
Fixed Rails Width
GND
Source Jan Rabaey
28
Layout Styles
Standard Cells
2-input NAND gate
Shared drain area and contact
A
B
Merged drain source area
Out
GND
Source Jan Rabaey
29
Layout Styles

• Stick Diagrams

• Contains no dimensions
• Represents relative positions of transistors

Inverter
NAND2
Out
Out
In
A
B
GND
GND
Source Jan Rabaey
30
Layout Styles

• X C (A B)

Logic Graph
Source Jan Rabaey
31
Layout Styles

• OAI22

X (AB)(CD)
Logic Graph
Source Jan Rabaey
32
Layout Planning using Euler Path approach

• Euler Path a path through all nodes in the
  graph such that each edge in the graph is only
  visited once
• Lead to uninterrupted diffusion strip if it has
  the same sequence for both PUN and PDN, i.e.
  consistent

Ex X C (A B)
X
C
i
X
VDD
A
B
j
GND
interrupted
Two Versions of C (A B)
Euler Path A-B-C
Source Jan Rabaey
33
Layout Planning using Euler Path approach

• X ABCD

Source Jan Rabaey
34
Layout Styles

• Multi-Fingered Transistors

Two fingers (folded)
Less diffusion capacitance
One finger
Source Jan Rabaey
35
CMOS Gates RC Delay

• Simple RC Model Delay depending on input
  patterns

A0,B0
A0,B1
A1,B1
tPLH 0.69(RP //RP )CL
tPLH 0.69RPCL
tPHL 0.69(2RN)CL
36
CMOS Gates

• Switching point depends on input patterns

Source Hodges
37
CMOS Gates

• Delay depends on input patterns

NMOS 0.5?m/0.25 ?m PMOS 0.75?m/0.25 ?m CL
100 fF
2-input NAND
Source Jan Rabaey
38
Static CMOS Gates Transistor Sizing

• Always match worst case delay of PUN and PDN

RPUN RPDN
Source Hodges
39
Complex CMOS Gates Sizing
Example
8W
B
4W
C
8W
4W
OUT D A (B C)
A
2W
D
W
2W
B
C
2W
Source Jan Rabaey
40
CMOS Gates Fan-in

• Fan-in the number of input of gate

Fan-in 4
A
Using distributed RC model (Elmore delay) tPHL
0.69 Reqn(C12C23C34CL) Propagation delay
deteriorates rapidly as a function of fan-in
quadratically in the worst case.
B
C
D
Source Jan Rabaey
41
CMOS Gates Fan-in

• tp as a function of fan-In

quadratic
tpHL
tp (psec)
tp
tpLH
linear
fan-in

• Gate with Fan-in more than 4 should be avoided.

Source Jan Rabaey
42
Large Fan-in Gate

• 8-input AND

Source Hodges
43
Large Fan-in Gate

• Use multi-level structure

Source Jan Rabaey